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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16304-1E
32-bit RISC Microcontroller
CMOS
FR Family MB91F109
MB91F109
s DESCRIPTION
The MB91F109 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To carry out hi-speed performance of CPU instructions, instruction/data Flash memory of 254 Kbytes and RAM of 2 Kbytes + 2 Kbytes are embedded in the MB91F109. The MB91F109 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers. *: FR Family stands for FUJITSU RISC controller.
s FEATURES
FR CPU 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency: Internal 25 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) General purpose registers: 32 bits x 16 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages * Register interlock functions, efficient assembly language coding * Branch instructions with delay slots: Reduced overhead time in branch executions * * * * * *
(Continued)
s PACKAGES
100-pin Plastic LQFP 100-pin Plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB91F109
(Continued) * Internal multiplier/supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles * Interrupt (push PC and PS): 6 cycles, 16 priority levels
External bus interface Without Clock doubler: Maximum internal bus 25 MHz, maximum external bus 25 MHz operation 25-bit address bus (32 Mbytes memory space) 8/16-bit data bus Basic external bus cycle: 2 clock cycles Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6 Interface supported for various memory technologies DRAM interface (area 4 and 5) * Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area * Unused data/address pins can be configured us input/output ports * Little endian mode supported (Select 1 area from area 1 to 5) DRAM interface 2 banks independent control (area 4 and 5) Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode * Supports 8/9/10/12-bit column address width * 2CAS/1WE, 2WE/1CAS selective DMA controller (DMAC) * * * * * * * * * * * * * * * * * * 2 8 channels Transfer incident/external pins/internal resource interrupt requests Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer Transfer data length: 8 bits/16 bits/32 bits selective NMI/interrupt request enables temporary stop operation 3 independent channels Full-duplex double buffer Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity) Asynchronous (start-stop system), CLK-synchronized communication selective Multi-processor mode Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate Use external clock can be used as a transfer clock Error detection: Parity, frame, overrun 10-bit resolution, 4 channels Successive approximation type: Conversion time of 5.6 s at 25 MHz Internal sample and hold circuit Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective Start: Software/external trigger/internal timer selective * * * * * * * * * * *
UART
10-bit A/D converter (successive approximation conversion type)
MB91F109
(Continued)
16-bit reload timer * 3 channels * Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective Other interval timers * 16-bit timer: 3 channels (U-TIMER) * PWM timer: 4 channels * Watchdog timer: 1 channel Bit search module First bit transition "1" or "0" from MSB can be detected in 1 cycle Interrupt controller * External interrupt input: Non-maskable interrupt (NMI), normal interrupt x 4 (INT0 to INT3) * Internal interrupt incident:UART, DMA controller (DMAC), 10-bit A/D converter, 16-bit reload-timer, PWM timer, U-TIMER and delayed interrupt module * Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps) Others * Reset cause: Power-on reset/software reset/external reset * Low-power consumption mode: Sleep mode/stop mode * Clock control Gear function: Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) (However, operating frequency for peripherals is less than 25 MHz.) * Packages: LQFP-100 and QFP-100 * CMOS technology (0.5 m) * Power supply voltage: 3.15 V 3.6 V
s PRODUCT LINEUP
Parameter Classification Flash size IRAM size CROM size CRAM size RAM size I$ Other Part number MB91F109 Mass production products Flash (mask ROM products) 254 Kbytes -- -- 2 Kbytes 2 Kbytes -- Under trial manufacture
3
4
MB91F109
s PIN ASSIGNMENT
CS1L/PB5/DREQ2 CS1H/PB6/DACK2 DW1/PB7 VCC CLK/PA6 CS5/PA5 CS4/PA4 CS3/PA3/EOP1 CS2/PA2 CS1/PA1 CS0/PA0 NMI VCC RST VSS MD0 MD1 MD2 RDY/P80 BGRNT/P81 BRQ/P82 RD/P83 WR0/P84 WR1/P85 D16/P20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (Top view)
(FPT-100P-M05)
D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24/P30 D25/P31 D26/P32 D27/P33 D28/P34 D29/P35 D30/P36 VSS D31/P37 A00/P40 VCC A01/P41 A02/P42 A03/P43 A04/P44 A05/P45 A06/P46 A07/P47 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/EOP0/P70 A23/P67 A22/P66 VSS A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 A16/P60 A15/P57 A14/P56 A13/P55 A12/P54 A11/P53 A10/P52 A09/P51 A08/P50
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RAS1/PB4/EOP2 DW0/PB3 CS0H/PB2 CS0L/PB1 RAS0/PB0 INT0/PE0 INT1/PE1 VCC X0 X1 VSS INT2/SC1/PE2 INT3/SC2/PE3 DREQ0/PE4 DREQ1/PE5 DACK0/PE6 DACK1/PE7 OCPA0/PF7/ATG SO2/OCPA2/PF6 SI2/OCPA1/PF5 SO1/TRG3/PF4 SI1/TRG2/PF3 SC0/OCPA3/PF2 SO0/TRG1/PF1 SI0/TRG0/PF0
MB91F109
(Top view)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 34 41 42 43 44 45 46 47 48 49 50
CS0L/PB1 RAS0/PB0 INT0/PE0 INT1/PE1 VCC X0 X1 VSS INT2/SC1/PE2 INT3/SC2/PE3 DREQ0/PE4 DREQ1/PE5 DACK0/PE6 DACK1/PE7 OCPA0/PF7/ATG SO2/OCPA2/PF6 SI2/OCPA1/PF5 SO1/TRG3/PF4 SI1/TRG2/PF3 SC0/OCPA3/PF2
CS0H/PB2 DW0/PB3 RAS1/PB4/EOP2 CS1L/PB5/DREQ2 CS1H/PB6/DACK2 DW1/PB7 VCC CLK/PA6 CS5/PA5 CS4/PA4 CS3/PA3/EOP1 CS2/PA2 CS1/PA1 CS0/PA0 NMI VCC RST VSS MD0 MD1 MD2 RDY/P80 BGRNT/P81 BRQ/P82 RD/P83 WR0/P84 WR1/P85 D16/P20 D17/P21 D18/P22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SO0/TRG1/PF1 SI0/TRG0/PF0 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/EOP0/P70 A23/P67 A22/P66 VSS A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 A16/P60 A15/P57 A14/P56 A13/P55 A12/P54 A11/P53 A10/P52 A09/P51 A08/P50 A07/P47 A06/P46 A05/P45
D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24/P30 D25/P31 D26/P32 D27/P33 D28/P34 D29/P35 D30/P36 VSS D31/P37 A00/P40 VCC A01/P41 A02/P42 A03/P43 A04/P44 (FPT-100P-M06)
5
MB91F109
s PIN DESCRIPTION
Pin no. LQFP*1 25 to 32 QFP*2 Pin name Circuit type C Function Bit 16 to bit 23 of external data bus Can be configured as general purpose I/O port when external data bus width is set to 8-bit or in single chip mode. C Bit 24 to bit 31 of external data bus Can be configured as general purpose I/O ports when not used as address bus. E Bit 00 to bit 15 of external address bus
28 to 35 D16 to D23 P20 to P27
33 to 39, 41
36 to 42, D24 to D30, 44 D31 P30 to P36, P37
42, 44 to 50, 51 to 58
45, A00, 47 to 53, A01 to A07, 54 to 61 A08 to A15 P40, P41 to P47, P50 to P57
Can be configured as general purpose I/O ports when not used as address bus. E Bit 16 to bit 23 of external address bus
59 to 64, 66, 67
62 to 67, A16 to A21, 69, A22, 70 A23 P60 to P65, P66, P67
Can be configured as general purpose I/O ports when not used as address bus. E Bit 24 of external address bus Can be configured as DMAC EOP output (ch. 0) when DMAC EOP output is enabled. Can be configured as general purpose I/O port when A24 and EOP0 are not used. C External ready input Inputs "0" when bus cycle is being executed and not completed. Can be configured as general purpose I/O port when RDY is not used. E External bus release acknowledge output Outputs "L" level when external bus is released. Can be configured as general purpose I/O port when BGRNT is not used. C External bus release request input Inputs "1" when release of external bus is required. Can be configured as general purpose I/O port when BRQ is not used. E Read strobe output pin for external bus Can be configured as general purpose I/O port when RD is not used.
68
71
A24 EOP0 P70
19
22
RDY P80
20
23
BGRNT P81
21
24
BRQ P82
22
25
RD P83
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
6
MB91F109
Pin no. LQFP* 23
1
QFP* 26
2
Pin name P84 WR0
Circuit type E
Function Can be configured as general purpose I/O port when WR0 is not used. Write strobe output pin for external bus Relation between control signals and effective byte locations is as follows:
24
27
WR1
E D31 to D24 D23 to D16
16-bit bus width WR0 WR1
8-bit bus width WR0 (I/O port enabled)
Single chip mode (I/O port enabled) (I/O port enabled)
Note : WR1 is Hi-Z during resetting. Attach an external pull-up resister when using at 16-bit bus width. P85 11 14 CS0 PA0 10 13 CS1 PA1 9 8 12 11 CS2 PA2 CS3 PA3 EOP1 E E E E Can be configured as general purpose I/O port when WR1 is not used. Chip select 0 output ("L" active) Can be configured as general purpose I/O port when CS0 is not used. Chip select 1 output ("L" active) Can be configured as general purpose I/O port when CS1 is not used. Chip select 2 output ("L" active) Can be configured as a port when CS2 is not used. Chip select 3 output ("L" active) Can be configured as a port when CS3 and EOP1 are not used. EOP output pin for DMAC (ch. 1) This function is available when EOP output for DMAC is enabled. E Chip select 4 output ("L" active) Can be configured as general purpose I/O port when CS4 is not used. E Chip select 5 output ("L" active) Can be configured as general purpose I/O port when CS5 is not used. E System clock output Outputs clock signal of external bus operating frequency. Can be configured as general purpose I/O port when CLK is not used.
7
10
CS4 PA4
6
9
CS5 PA5
5
8
CLK PA6
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
7
MB91F109
Pin no. LQFP* 96
1
QFP* 99
2
Pin name RAS0 PB0
Circuit type E
Function RAS output for DRAM bank 0 Can be configured as general purpose I/O port when RAS0 is not used.
97
100
CS0L PB1
E
CASL output for DRAM bank 0 Can be configured as general purpose I/O port when CS0L is not used.
98
1
CS0H PB2
E
CASH output for DRAM bank 0 Can be configured as general purpose I/O port when CS0H is not used.
99
2
DW0 PB3
E
WE output for DRAM bank 0 ("L" active) Can be configured as general purpose I/O port when DW0 is not used.
100
3
RAS1 PB4 EOP2
E
RAS output for DRAM bank 1 Can be configured as general purpose I/O port when RAS1 and EOP2 are not used. DMAC EOP output (ch. 2) This function is available when DMAC EOP output is enabled.
1
4
CS1L PB5 DREQ2
E
CASL output for DRAM bank 1 Can be configured as general purpose I/O port when CS1L and DREQ are not used. External transfer request input pin for DMA This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.
2
5
CS1H PB6 DACK2
E
CASH output for DRAM bank 1 Can be configured as general purpose I/O port when CS1H and DACK2 are not used. External transfer request accept output pin for DMAC (ch. 2) This function is available when transfer request output for DMAC is enabled.
3
6
DW1 PB7
E
WE output for DRAM bank 1 ("L" active) Can be configured as general purpose I/O port when DW1 is not used.
16 to 18
19 to 21 MD0 to MD2
F
Mode pins 0 to 2 MCU basic operation mode is set by these pins. Directly connect these pins with VCC or VSS for use. Clock (oscillator) input Clock (oscillator) output External reset input NMI (non-maskable interrupt pin) input ("L" active)
92 91 14 12
95 94 17 15
X0 X1 RST NMI
A A B G
*1: FPT-100P-M05 *2: FPT-100P-M06 8
(Continued)
MB91F109
Pin no. LQFP* 95, 94
1
QFP* 98, 97
2
Pin name INT0, INT1
Circuit type E
Function External interrupt request input pins These pins are used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. Can be configured as general purpose I/O ports when INT0 and INT1 are not used.
PE0, PE1 89 92 INT2 E
External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. Clock I/O pin for UART1 Clock output is available when clock output of UART1 is enabled. Can be configured as general purpose I/O port when INT2 and SC1 are not used. This function is available when UART1 clock output is disabled.
SC1
PE2
88
91
INT3
E
External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. UART2 clock I/O pin Clock output is available when UART2 clock output is enabled. Can be configured as general purpose I/O port when INT3 and SC2 are not used. This function is available when UART2 clock output is disabled.
SC2 PE3
87, 86
90, 89
DREQ0, DREQ1
E
External transfer request input pins for DMA These pins are used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. Can be configured as general purpose I/O ports when DREQ0 and DREQ1 are not used.
PE4, PE5 85 88 DACK0 E
External transfer request acknowledge output pin for DMAC (ch. 0) This function is available when transfer request output for DMAC is enabled. Can be configured as general purpose I/O port when DACK0 is not used. This function is available when transfer request acknowledge output for DMAC or DACK0 output is disabled.
PE6
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
9
MB91F109
Pin no. LQFP* 84
1
QFP* 87
2
Pin name DACK1
Circuit type E
Function External transfer request acknowledge output pin for DMAC (ch. 1) This function is available when transfer request output for DMAC is enabled. Can be configured as general purpose I/O port when DACK1 is not used. This function is available when transfer request output for DMAC or DACK1 output is disabled.
PE7
76
79
SI0
E
UART0 data input pin This pin is used for input during UART0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PWM timer external trigger input pin (ch.0) This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. Can be configured as general purpose I/O port when SI0 and TRG0 are not used.
TRG0
PF0 77 80 SO0 TRG1 E
UART0 data output pin This function is available when UART0 data output is enabled. PWM timer external trigger input pin This function is available when serial data output of PF1, UART0 are disabled. Can be configured as general purpose I/O port when SO0 and TRG1 are not used. This function is available when serial data output of UART0 is disabled.
PF1
78
81
SC0 OCPA3 PF2
E
UART0 clock I/O pin Clock output is available when UART0 clock output is enabled. PWM timer output pin This function is available when PWM timer output is enabled. Can be configured as general purpose I/O port when SC0 and OCPA3 are not used. This function is available when UART0 clock output is disabled.
79
82
SI1
E
UART1 data input pin This pin is used for input during UART1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PWM timer external trigger input pin This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. Can be configured as general purpose I/O port when SI1 and TRG2 are not used.
TRG2
PF3 *1: FPT-100P-M05 *2: FPT-100P-M06 10
(Continued)
MB91F109
Pin no. LQFP*1 80 QFP*2 83
Pin name SO1 TRG3
Circuit type E
Function UART1 data output pin This function is available when UART1 data output is enabled. PWM timer external trigger input pin This function is available when PF4, UART1 data outputs are disabled. Can be configured as general purpose I/O port when SO1 and TRG3 are not used. This function is available when UART1 data output is disabled.
PF4
81
84
SI2
E
UART2 data input pin This pin is used for input during UART2 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PWM timer output pin This function is available when PWM timer output is enabled. Can be configured as general purpose I/O port when SI2 and OCPA2 are not used.
OCPA1 PF5 82 85 SO2 OCPA2 PF6 E
UART2 data output pin This function is available when UART2 data output is enabled. PWM timer output pin This function is available when PWM timer output is enabled. Can be configured as general purpose I/O port when SO2 and OCPA2 are not used. This function is available when UART2 data output is disabled.
83
86
OCPA0 PF7
E
PWM timer output pin This function is available when PWM timer output is enabled. Can be configured as a port when OCPA0 and ATG are not used. This function is available when PWM timer output is disabled. External trigger input pin for A/D converter This pin is used for input when external trigger is selected to cause A/D converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.
ATG
72 to 75 69 70
75 to 78 AN0 to AN3 72 73 AVCC AVRH
D -- --
Analog input pins of A/D converter Power supply pin (VCC) for A/D converter Reference voltage input (high) for A/D converter Make sure to turn on and off this pin with potential of AVRH or more applied to VCC. Power supply pin (VSS) for A/D converter and reference voltage input pin (low)
71
74
AVSS, AVRL
--
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
11
MB91F109
(Continued)
Pin no. LQFP* 4, 13, 43, 93 15, 40, 65, 90
1
QFP* 7, 16, 46, 96 18, 43, 68, 93
2
Pin name VCC
Circuit type --
Function Power supply pin (VCC) for digital circuit Always power supply pin (VCC) must be connected to the power supply Earth level (VSS) for digital circuit
VSS
--
*1: FPT-100P-M05 *2: FPT-100P-M06 Note : In most of the above pins, I/O port and resource I/O are multiplexed e.g. xxx/Pxxx. In case of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O.
12
MB91F109
s DRAM CONTROL PIN
Pin name RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1 Data bus 16-bit mode 2CAS/1WR mode Area 4 RAS Area 5 RAS Area 4 CASL Area 4 CASH Area 5 CASL Area 5 CASH Area 4 WE Area 5 WE 1CAS/2WR mode Area 4 RAS Area 5 RAS Area 4 CAS Area 4 WEL Area 5 CAS Area 5 WEL Area 4 WEH Area 5 WEH Data bus 8-bit mode Area 4 RAS Area 5 RAS Area 4 CAS Area 4 CAS Area 5 CAS Area 5 CAS Area 4 WE Area 5 WE Remarks Correspondence of "L" "H" to lower address 1 bit (A0) in data bus 16bit mode "L": "0" "H": "1" CASL: CAS which A0 corresponds to "0" area CASH: CAS which A0 corresponds to "1" area WEL: WE which A0 corresponds to "0" area WEH: WE which A0 corresponds to "1" area
13
MB91F109
s I/O CIRCUIT TYPE
Type A
X1 Clock input
Circuit
Remarks * Oscillation feedback resistance 1 M approx. With standby control
X0
Standby control signal
B
VCC P-ch P-channel type transistor N-channel type transistor VSS Digital input
* CMOS level hysteresis input Without standby control With pull-up resistance
Diffused resistor
C
* CMOS level I/O With standby control
P-ch Digital output
R
N-ch
Digital output
Digital input Standby control signal
D
Digital output
* Analog input
P-ch
R
N-ch
Digital output
Analog input
(Continued)
14
MB91F109
(Continued)
Type E
Digital output
Circuit
Remarks * CMOS level output * CMOS level hysteresis input With standby control
P-ch N-ch
R
Digital output
Digital input Standby control signal
F
N-ch
* CMOS level input Without standby control
R
N-ch
Digital input
G
P-ch
* CMOS level hysteresis input Without standby control
R
N-ch
Digital input
15
MB91F109
s HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over rating across VCC and VSS may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating. Take care that the analog power supply (AVCC, AVRH) and the analog input do not exceed the digital power supply (VCC) when the analog power supply turned on or off.
2. Treatment of Unused Pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
3. External Reset Input
It takes at least 5 machine cycle to input "L" level to the RST pin and to ensure inner reset operation properly.
4. Remarks for External Clock Operation
When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at "H" output in stop mode). And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than. * Using an external clock
X0 X1 MB91F109
Using an external clock (normal) Note: Can not be used stop mode (oscillation stop mode).
X0 Open X1 MB91F109
Using an external clock (can be used at 12.5 MHz and less than.) (3.3 V power supply only)
16
MB91F109
5. Power Supply Pins
When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND. It is preferred to connect VCC and VSS of MB91F109 to power supply with minimal impedance possible. It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 F between VCC and VSS at a position as close as possible to MB91F109.
6. Crystal Oscillator Circuit
Noises around X0 and X1 pins may cause malfunctions of MB91F109. In designing the PC board, layout X0, X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for stable operation.
7. Turning-on Sequence of A/D Converter Power Supply and Analog Input
Make sure to turn on the digital power supply (VCC) before turning on the A/D converter (AVCC, AVRH) and applying voltage to analog input (AN0 to AN3). Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies may be turned on simultaneously.) Make sure that AVRH never exceeds AVCC when turning on/off power supplies.
8. Treatment of N.C. Pins
Make sure to leave N.C. pins open.
9. Fluctuation of Power Supply Voltage
Warranty range for normal operation against fluctuation of power supply voltage VCC is as given in rating. However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended that by controlling power supply as a reference of stabilizing, VCC ripple fluctuation (P-P value) at the commercial frequency (50 Hz to 60 Hz) should be less than 10% of the standard VCC value and the transient regulation should be less than 0.1 V/ms at instantaneous deviation like turning off the power supply.
10. Mode Setting Pins (MD0 to MD2)
Connect mode setting pins (MD0 to MD2) directly to VCC or VSS. Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.
11. Turning on the Power Supply
When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to "H" level.
17
MB91F109
12. Pin Condition at Turning on the Power Supply
The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation of the internal regulator becomes stable. So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz. Take care that the pin condition may be output condition at initial unstable condition.
13. Source Oscillation Input at Turning on the Power Supply
At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting.
14. Initialization
Some internal resistors initialized only via power on reset are embedded in the device. To initialize these resistors, run power on reset by returning on the power supply or to set RST pin to "H" level.
18
MB91F109
s BLOCK DIAGRAM
FR CPU
RAM (2 Kbytes) D-bus (32 bits)
Bit search module DREQ0 to DREQ2 DACK0 to DACK2 EOP0 to EOP2 3 3 3 DMA controller (DMAC) (8 ch.)
Bus converter (HarvardPrinceton)
16 25 Bus converter (32 bits16bits) Bus controller 2 6
X0 X1 RST
Clock control unit (Watchdog timer)
D16 to D31 A00 to A24 RD WR0, WR1 RDY CLK CS0 to CS5 BRQ BGRNT
AN0 to AN3 AVCC AVSS AVRH AVRL ATG
4
C-bus (32 bits)
INT0 to INT3 NMI
4 Interrupt control unit
DRAM interface
10-bit A/D converter (4 ch.) R-bus (16 bits)
RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1
Flash memory 254k
16-bit reload timer (3 ch.)
RAM 2 Kbytes
8 8
PE0 to PE7 PF0 to PF7
8 8
Port E, Port F
Port 2 to port B
8 8 8 6 7 8
P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 PA80 to P85 PA0 to PA6 PB0 to PB7 SI0 to SI2 SO0 to SO2 SC0 to SC2
Other pins UART (3 ch.) (Baud rate timer) MD0 to MD2, VCC, VSS
3 3 3
PWM timer (4 ch.)
4 4
OCPA0 to OCPA3 TRG0 to TRG3
Note : Pins are display for functions (Actually some pins are multiplexer). When using REALOS, time control should be done by using external interrupt or inner timer. 19
MB91F109
s CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory space. * Memory space
* Memory Space
Address
0000 0000H
Single chip mode I/O Area
Internal ROM/ external bus mode I/O Area I/O Area Access inhibited RAM 2 Kbytes
External ROM/ external bus mode I/O Area I/O Area Access inhibited RAM 2 Kbytes Direct addressing area*
0000 0400H
See "sI/O MAP"
I/O Area
0000 0800H
Access inhibited
0000 1000H
RAM 2 Kbytes
0000 1800H
Access inhibited
0001 0000H
Access inhibited
Access inhibited
Access inhibited
0008 0000H
External area Access inhibited RAM 2 Kbytes FLASH ROM 254 Kbytes External area External area
Access inhibited
000C 0000H
RAM 2 Kbytes
000C 0800H 0010 0000H FFFF FFFFH
FLASH ROM 254 Kbytes Access inhibited
*: Direct addressing area The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an address can be specified in a direct operand of a code. Direct areas consists of the following areas dependent on accessible data sizes. Byte data access: 000H to 0FFH Half word data access: 000H to 1FFH Word data access: 000H to 3FFH Notes: Access to the external area can be execute in the single chip mode. To access to the external area, select internal ROM external bus mode via mode resistor. Never execute data access to the instruction ROM area.
20
MB91F109
2. Registers
The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose registers on memory. * Dedicated registers 32-bit length, indicates the location of the instruction to be executed. 32-bit length, register for storing register pointer or condition codes Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap) processing. Return pointer (RP): Holds address to resume operation after returning from a subroutine. System stack pointer (SSP): Indicates system stack space. User's stack pointer (USP): Indicates user's stack space. Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division Program counter (PC): Program status (PS): Table base register (TBR):
32 bits PC PS TBR RP SSP USP MDH MDL Program counter Program status Table base register Return pointer System stack pointer User's stack pointer
Initial value XXXX XXXXH
Indeterminate
000F
FC00H Indeterminate
XXXX XXXXH 0000 0000H
XXXX XXXXH XXXX XXXXH XXXX XXXXH
Indeterminate Indeterminate Indeterminate
Multiplication/division result register
* Program status (PS) The PS register is for holding program status and consists of a condition code register (CCR), a system condition code register (SCR) and a interrupt level mask register (ILM).
31 PS --
20
19
18
17
16 --
10 D1
9 D0
8 T
7 --
6 --
5 S
4 I
3 N
2 Z
1 V
0 C
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
SCR
CCR
21
MB91F109
* Condition code register (CCR) S-flag: I-flag: N-flag: Z-flag: V-flag: C-flag: Specifies a stack pointer used as R15. Controls user interrupt request enable/disable. Indicates sign bit when division result is assumed to be in the 2's complement format. Indicates whether or not the result of division was "0". Assumes the operand used in calculation in the 2's complement format and indicates whether or not overflow has occurred. Indicates if a carry or borrow from the MSB has occurred.
* System condition code register (SCR) T-flag: Specifies whether or not to enable step trace trap.
* Interrupt level mask register (ILM) ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 0 ILM3 0 ILM2 0 : : 0 1 0 : : 1 1 1 1 1 0 0 ILM1 0 ILM0 0 Interrupt level 0 : : 15 : : 31 Low High-low High
22
MB91F109
s GENERAL-PURPOSE REGISTERS
R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer (field for indicating address). * Register bank structure
32 bits Initial value R0 R1 : : R12 R13 R14 R15 AC (accumulator) FP (frame pointer) SP (stack pointer) XXXX XXXXH : : : : : : : : : : : XXXX XXXXH 0 0 0 0 0 0 0 0H
Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13: Virtual accumulator (AC) R14: Frame pointer (FP) R15: Stack pointer (SP) Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value).
23
MB91F109
s SETTING MODE
1. Pin
* Mode setting pins and modes Mode setting pins MD2 MD1 MD0 0 0 0 0 1 0 0 1 1 -- 0 1 0 1 -- External vector mode 0 External vector mode 1 -- Internal vector mode -- Mode name Reset vector access area External External -- Internal -- External data bus width 8 bits 16 bits -- (Mode register) -- Bus mode External ROM/external bus mode Inhibited Single-chip mode* Not use
*: MB91F109 support single-chip mode.
2. Registers
* Mode setting registers (MODR) and modes
Address 0000 07FFH M1 M0 * * * * * *
Initial value XXXX XXXXB
Access W
Bus mode setting bit W : Write only X : Indeterminate * : Always write "0" except for M1 and M0.
* Bus mode setting bits and functions M1 0 0 1 1 M0 0 1 0 1 Single-chip mode Internal ROM/external bus mode External ROM/external bus mode -- Inhibited Functions Note
24
MB91F109
s I/O MAP
Address Register name (abbreviated) Register name Port 3 data register Port 2 data register (Vacancy) Port 7 data register Port 6 data register Port 5 data register Port 4 data register Port B data register Port A data register (Vacancy) Port 8 data register (Vacancy) Port E data register Port F data register (Vacancy) Serial status register 0 Serial input data register 0/serial output data register 0 Serial control register 0 Serial mode register 0 Serial status register 1 Serial input data register 1/serial output data register 1 Serial control register 1 Serial mode register 1 Serial status register 2 Serial input data register 2/serial output data register 2 Serial control register 2 Serial mode register 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UART2 UART1 UART0 00001-00B XXXXXXXXB 00000100B 00--0-00B 00001-00B XXXXXXXXB 00000100B 00--0-00B 00001-00B XXXXXXXXB 00000100B 00--0-00B R/W R/W Port E Port F XXXXXXXXB XXXXXXXXB R/W Port 8 - - XXXXXXB R/W R/W R/W R/W R/W R/W Port 7 Port 6 Port 5 Port 4 Port B Port A -------XB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - XXXXXXXB Read/write R/W R/W Resources name Port 3 Port 2 Initial value XXXXXXXXB XXXXXXXXB
000000H PDR3 000001H PDR2 000002H 000003H 000004H PDR7 000005H PDR6 000006H PDR5 000007H PDR4 000008H PDRB 000009H PDRA 00000AH 00000BH PDR8 00000CH to 000011H 000012H PDRE 000013H PDRF 000014H to 00001BH 00001CH SSR0 00001DH SIDR0/SODR0 00001EH SCR0 00001FH SMR0 000020H SSR1 000021H SIDR1/SODR1 000022H SCR1 000023H SMR1 000024H SSR2 000025H SIDR2/SODR2 000026H SCR2 000027H SMR2
(Continued)
25
MB91F109
Address 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H to 000077H
Register name (abbreviated) TMRLR0 TMR0
Register name 16-bit reload register 0 16-bit timer register 0 (Vacancy)
Read/write W
Resources name
Initial value XXXXXXXXB
16-bit reload timer 0 R
XXXXXXXXB XXXXXXXXB XXXXXXXXB
TMCSR0 TMRLR1 TMR1
16-bit reload timer control status register 0 16-bit reload register 1 16-bit timer register 1 (Vacancy)
R/W W R
16-bit reload timer 0 16-bit reload timer 1
----0000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
TMCSR1 ADCR ADCS TMRLR2 TMR2
16-bit reload timer control status register 1 A/D converter data register A/D converter control status register 16-bit reload register 2 16-bit timer register 2 (Vacancy)
R/W R
16-bit reload timer 1
----0000B 00000000B 0 0 0 0 0 0XXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
10-bit A/D converter R/W W 16-bit reload timer 2 R
TMCSR2
16-bit reload timer control status register 2 (Vacancy)
R/W
16-bit reload timer 2
----0000B 00000000B
(Continued)
26
MB91F109
Address 000078H 000079H 00007AH
Register name (abbreviated) UTIM0/UTIMR0
Register name U-TIMER register ch. 0 /U-TIMER reload register ch. 0 (Vacancy) U-TIMER control register ch. 0 U-TIMER register ch. 1/reload register ch. 1 (Vacancy) U-TIMER control register ch. 1 U-TIMER register ch. 2/U-TIMER reload register ch. 2 (Vacancy) U-TIMER control register ch. 2 (Vacancy) External interrupt cause register Interrupt enable register (Vacancy) External interrupt request level setting register (Vacancy) Port E data direction register Port F data direction register (Vacancy)
Read/write R/W
Resources name U-TIMER 0
Initial value 00000000B 00000000B 0--00001B 00000000B 00000000B 0--00001B 00000000B 00000000B 0--00001B
00007BH UTIMC0 00007CH 00007DH 00007EH 00007FH UTIMC1 000080H 000081H 000082H 000083H UTIMC2 000084H to 000093H 000094H EIRR 000095H ENIR 000096H to 000098H 000099H ELVR 00009AH to 0000D1H 0000D2H DDRE 0000D3H DDRF 0000D4H to 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH GCN2 GCN1 UTIM2/UTIMR2 UTIM1/UTIMR1
R/W R/W
U-TIMER 0 U-TIMER 1
R/W R/W
U-TIMER 1 U-TIMER 2
R/W
U-TIMER 2
R/W R/W
External interrupt/ NMI
00000000B 00000000B
R/W
External interrupt/ NMI
00000000B
W W
Port E Port F
00000000B 00000000B
General control register 1 (Vacancy) General control register 2
R/W
PWM timer 1
00110010B 00010000B
R/W
PWM timer 2
00000000B
(Continued)
27
MB91F109
Address 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H
Register name (abbreviated) PTMR0 PCSR0 PDUT0
Register name PWM timer register 0 PWM cycle setting register 0 PWM duty setting register 0 Control status register H 0 Control status register L 0 PWM timer register 1 PWM cycle setting register 1 PWM duty setting register 1 Control status register H 1 Control status register L 1 PWM timer register 2 PWM cycle setting register 2 PWM duty setting register 2 Control status register H 2 Control status register L 2 PWM timer register 3 PWM cycle setting register 3 PWM duty setting register 3 Control status register H 3 Control status register L 3
Read/write R W
Resources name
Initial value 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000-B 00000000B 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000-B 00000000B 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000-B 00000000B 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000-B 00000000B
PWM timer 0 W R/W R/W R W PWM timer 1 PDUT1 W R/W R/W R W PWM timer 2 PDUT2 W R/W R/W R W PWM timer 3 PDUT3 W R/W R/W
0000E6H PCNH0 0000E7H PCNL0 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH PTMR1 PCSR1
0000EEH PCNH1 0000EFH PCNL1 0000F0H 0000F1H 0000F2H 0000F3H 0000F4H 0000F5H PTMR2 PCSR2
0000F6H PCNH2 0000F7H PCNL2 0000F8H 0000F9H 0000FAH 0000FBH 0000FCH 0000FDH PTMR3 PCSR3
0000FEH PCNH3 0000FFH PCNL3
(Continued)
28
MB91F109
Address 000100H to 0001FFH 000200H 000201H 000202H 000203H 000204H 000205H 000206H 000207H 000208H 000209H 00020AH 00020BH 00020CH to 0003EFH 0003F0H 0003F1H 0003F2H 0003F3H 0003F4H 0003F5H 0003F6H 0003F7H 0003F8H 0003F9H 0003FAH 0003FBH 0003FCH 0003FDH 0003FEH 0003FFH
Register name (abbreviated)
Register name (Vacancy)
Read/write
Resources name
Initial value
XXXXXXXXB DPDP DMAC parameter descriptor pointer R/W XXXXXXXXB XXXXXXXXB X0000000B 00000000B DACSR DMAC control status register R/W DMA controller (DMAC) 00000000B 00000000B 00000000B XXXXXXXXB DATCR DMAC pin control register R/W XX0 0 0 0 0 0 B XX0 0 0 0 0 0 B XX0 0 0 0 0 0 B (Vacancy) XXXXXXXXB BSD0 Bit search module 0-detection data register R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB BSD1 Bit search module 1-detection data register R/W Bit search module BSDC Bit search module transitiondetection data register W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB BSRR Bit search module detection result register R XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
29
MB91F109
Address
Register name (abbreviated)
Register name Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt control register 3 Interrupt control register 4 Interrupt control register 5 Interrupt control register 6 Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Interrupt control register 16 Interrupt control register 17 Interrupt control register 18 Interrupt control register 19 Interrupt control register 20 Interrupt control register 21 Interrupt control register 22 Interrupt control register 23 Interrupt control register 24 Interrupt control register 25 Interrupt control register 26 Interrupt control register 27 Interrupt control register 28 Interrupt control register 29 Interrupt control register 30 Interrupt control register 31
Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resources name
Initial value ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B
000400H ICR00 000401H ICR01 000402H ICR02 000403H ICR03 000404H ICR04 000405H ICR05 000406H ICR06 000407H ICR07 000408H ICR08 000409H ICR09 00040AH ICR10 00040BH ICR11 00040CH ICR12 00040DH ICR13 00040EH ICR14 00040FH ICR15 000410H ICR16 000411H ICR17 000412H ICR18 000413H ICR19 000414H ICR20 000415H ICR21 000416H ICR22 000417H ICR23 000418H ICR24 000419H ICR25 00041AH ICR26 00041BH ICR27 00041CH ICR28 00041DH ICR29 00041EH ICR30 00041FH ICR31
Interrupt controller
(Continued)
30
MB91F109
Address 000420H to 00042EH
Register name (abbreviated)
Register name (Vacancy) Interrupt control register 47 Delayed interrupt control register Hold request cancel request level setting register (Vacancy) Reset cause register/ watchdog cycle control register Standby control register DMA controller request squelch register Timebase timer clear register Gear control register Watchdog reset occurrence postpone register (Vacancy) PLL control register (Vacancy) Port 3 data direction register Port 2 data direction register (Vacancy) Port 7 data direction register Port 6 data direction register Port 5 data direction register Port 4 data direction register Port B data direction register Port A data direction register (Vacancy) Port 8 data direction register
Read/write
Resources name
Initial value
00042FH ICR47 000430H DICR 000431H HRCL 000432H to 00047FH 000480H RSRR/WTCR 000481H STCR 000482H PDRR 000483H CTBR 000484H GCR 000485H WPR 000486H 000487H 000488H PCTR 000489H to 0005FFH 000600H DDR3 000601H DDR2 000602H 000603H 000604H DDR7 000605H DDR6 000606H DDR5 000607H DDR4 000608H DDRB 000609H DDRA 00060AH 00060BH DDR8
R/W R/W R/W Interrupt controller
---11111B -------0B ---11111B
R/W R/W R/W W R/W W Clock generator
1X X X X - 0 0
B
000111--B ----0000B XXXXXXXXB 110011-1B XXXXXXXXB
R/W
PLL control
00--0---B
W W
Port 3 Port 2
00000000B 00000000B
W W W W W W W
Port 7 Port 6 Port 5 Port 4 Port B Port A Port 8
-------0B 00000000B 00000000B 00000000B 00000000B -0000000B --000000B
(Continued)
31
MB91F109
Address 00060CH 00060DH 00060EH 00060FH 000610H 000611H 000612H 000613H 000614H 000615H 000616H 000617H 000618H 000619H 00061AH 00061BH 00061CH 00061DH 00061EH 00061FH
Register name (abbreviated) ASR1 AMR1 ASR2 AMR2 ASR3 AMR3 ASR4 AMR4 ASR5 AMR5
Register name Area select register 1 Area mask register 1 Area select register 2 Area mask register 2 Area select register 3 Area mask register 3 Area select register 4 Area mask register 4 Area select register 5 Area mask register 5 Area mode register 0 Area mode register 1 Area mode register 32 Area mode register 4 Area mode register 5 DRAM signal control register Refresh control register External pin control register 0 External pin control register 1 DRAM control register 4 DRAM control register 5
Read/write W W W W W W W W W W R/W R/W R/W R/W R/W W R/W W W R/W R/W
Resources name
Initial value 00000000B 00000001B 00000000B 00000000B 00000000B 00000010B 00000000B 00000000B 00000000B 00000011B 00000000B 00000000B 00000000B 00000100B 00000000B 00000000B 00000000B
External bus 0 0 0 0 0 1 0 1 B interface 00000000B 00000000B ---00111B 0--00000B 00000000B 0--00000B 0--00000B 00000000B - -XXXXXXB 00---000B ----1100B -1111111B -------1B 11111111B 00000000B 0000000-B 00000000B 0000000-B
000620H AMD0 000621H AMD1 000622H AMD32 000623H AMD4 000624H AMD5 000625H DSCR 000626H 000627H 000628H 000629H 00062AH 00062BH 00062CH 00062DH 00062EH 00062FH RFCR EPCR0 EPCR1 DMCR4 DMCR5
(Continued)
32
MB91F109
(Continued)
Address 000630H to 0007BFH 0007C0H FSTR 0007C1H to 0007FDH 0007FEH LER 0007FFH MODR Little endian register Mode register Register name (abbreviated) Register name (Vacancy) FLASH memory status register (Vacancy) W W External bus - - - - - 0 0 0 B interface XXXXXXXXB R/W FLASH memory 0 0 0 XXXX 0 B Read/write Resources name Initial value
About Programming R/W: Readable and writable R: Read only W: Write only Explanation of initial values 0: 1: X: -: The initial value of this bit is "0". The initial value of this bit is "1". The initial value of this bit is undefined. This bit is not used. The initial value of this bit is undefined. Rj, @ Ri Rj, @ Ri Rj, @ Ri #4, @ Ri #4, @ Ri
RMW system instructions (RMW: Read Modify Write) AND Rj, @ Ri OR Rj, @ Ri EOR ANDH Rj, @ Ri ORH Rj, @ Ri EORH ANDB Rj, @ Ri ORB Rj, @ Ri EORB BANDL #4, @ Ri BORL #4, @ Ri BEORL BANDH #4, @ Ri BORH #4, @ Ri BEORH
Notes: * Never execute a RMW system instruction to the resistor has a write only bit. * The area "vacancy" on the I/O map is reserved area. Access to this area are deal with to an internal area. No access signals to the external area would be generated.
33
MB91F109
s INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes Reset Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Exception for undefined instruction NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 UART0 receive complete UART1 receive complete UART2 receive complete UART0 transmit complete UART1 transmit complete UART2 transmit complete DMAC0 (complete, error) DMAC1 (complete, error) DMAC2 (complete, error) DMAC3 (complete, error) DMAC4 (complete, error) DMAC5 (complete, error) Interrupt number Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Interrupt level Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H
(Continued)
34
MB91F109
Interrupt causes DMAC6 (complete, error) DMAC7 (complete, error) A/D converter (successive approximation conversion type) 16-bit reload timer 0 16-bit reload timer 1 16-bit reload timer 2 PWM 0 PWM 1 PWM 2 PWM 3 U-TIMER 0 U-TIMER 1 U-TIMER 2 FLASH memory Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Delayed interrupt cause bit
Interrupt number Decimal 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Hexadecimal 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
Interrupt level Register ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ICR47 Offset 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H
TBR default address 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H
(Continued)
35
MB91F109
(Continued)
Interrupt causes Reserved for system (used in REALOS*) Reserved for system (used in REALOS*) Used in INT instructions Interrupt number Decimal 64 65 66 to 255 Hexadecimal 40 41 42 to FF Interrupt level Register -- -- -- Offset 2FCH 2F8H 2F4H to 000H TBR default address 000FFEFCH 000FFEF8H 000FFEF4H to 000FFD00H
*: When using in REALOS/FR, interrupt 0x40, 0x41 for system code.
36
MB91F109
s PERIPHERAL RESOURCES
1. I/O Ports
There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register (DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/ output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. Bit "0" specifies input and "1" specifies output. * For input (DDR = "0") setting; PDR reading operation: reads level of corresponding external pin. PDR writing operation: writes set value to PDR. * For output (DDR = "1") setting; PDR reading operation: reads PDR value. PDR writing operation: outputs PDR value to corresponding external pin. (1) Register configuration * Port data register
Address 000001H 000000H 000007H 000006H 000005H 000004H 00000BH 000009H 000008H 000012H 000013H bit 7 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDRA PDRB PDRE PDRF bit 0 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX - - - - - - -X - - XXXXXX - XXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
B
B
B
B
B
B
B
B
B
B
( ) : Access R/W : Readable and writable X : Indeterminate
37
MB91F109
* Data direction register
Address 000601H 000600H 000607H 000606H 000605H 000604H 00060BH 000609H 000608H 0000D2H 0000D3H ( ) : Access W : Write only - : Unused bit 7 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDRA DDRB DDRE DDRF bit 0 Initial value 00000000 00000000 00000000 00000000 00000000 -------0 - - 000000 - 0000000 00000000 00000000 00000000
B
(W) (W) (W) (W) (W) (W) (W) (W) (W) (W) (W)
B
B
B
B
B
B
B
B
B
B
(2) Block diagram
Resource input
0
1 PDR read Data bus 0 PDR (Port data register) Resource output 1 Pin
Resource output enable DDR (Data direction register)
38
MB91F109
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. 8 channels Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer Transfer all through the area Max. 65536 of transfer cycles Interrupt function right after the transfer Selectable for address transfer increase/decrease by the software External transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each (1) Registers configuration * DMAC internal registers * DMAC parameter descriptor pointer
Address 00000200H bit 31 DPDP bit 0 Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B X0000000 B Initial value 00000000B 00000000B 00000000B 00000000B Initial value XXXXXXXX XX0 0 0 0 0 0 XX0 0 0 0 0 0 XX0 0 0 0 0 0
B B B B
* * * * * * *
(R/W)
* DMAC control status register
Address 00000204H bit 31 DACSR bit 0
(R/W)
* DMAC pin control register
Address 00000208H bit 31 DATCR bit 0
(R/W)
( ) : Access R/W : Readable and writable X : Indeterminate
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MB91F109
* DMAC descriptor
* The first word of descriptor
bit 31 DMACT bit 16 (R/W)
bit 15 -
bit 11 BLK
bit 8 bit 7
bit 0 (R/W)
* The second word of descriptor
bit 31 SADR bit 0 (R/W)
* The third word of descriptor
bit 31 DADR bit 0 (R/W)
R/W: Readable and writable
40
MB91F109
(2) Block diagram
DREQ0 to DREQ2
3
Edge/level detection circuit
3
3 3 Sequencer 8
DACK0 to DACK2 EOP0 to EOP2 Interrupt request
Inner resource Transfer request
5
Data buffer
Switcher
DMAC parameter descriptor pointer (DPDP)
DMAC control status register (DACSR)
DMAC pin control register (DATCR)
Mode
BLK DEC
BLK
The first word of descriptor (DMACT)
The second word of descriptor (SADR)
INC / DEC
The third word of descriptor (DADR)
Data bus
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MB91F109
3. UART
The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features. The MB91F109 consists of 3 channels of UART. Full double double buffer Both a synchronous (start-stop system) communication and CLK synchronous communication are available. Supporting multi-processor mode Perfect programmable baud rate Any baud rate can be set by internal timer (refer to section "4. U-TIMER"). * Any baud rate can be set by external clock. * Error checking function (parity, framing and overrun) * Transfer signal: NRZ code * Enable DMA transfer/start by interrupt. (1) Register configuration * Serial control register 0 to 2
Address SCR0 : 00001EH SCR1 : 000022H SCR2 : 000026H bit 15 SCR0 to SCR2 bit 8 bit 7 (SMR) bit 0 Initial value 00000100
B
* * * *
(R/W)
* Serial model register 0 to 2
Address SMR0 : 00001FH SMR1 : 000023H SMR2 : 000027H bit 15 (SCR) bit 8 bit 7 SMR0 to SMR2 bit 0 Initial value 00- - 0- 00
B
(R/W)
* Serial status register 0 to 2
Address SSR0 : 00001CH SSR1 : 000020H SSR2 : 000024H bit 15 SSR0 to SSR2 bit 8 bit 7 (SIDR) bit 0 Initial value 00001- 00
B
(R/W)
* Serial input data register 0 to 2
Address SIDR0 : 00001DH SIDR1 : 000021H SIDR2 : 000025H bit 15 (SSR) bit 8 bit 7 SIDR0 to SIDR2 bit 0 Initial value X X X X X X X X B (R)
* Serial output data register 0 to 2
Address SODR0 : 00001DH SODR1 : 000021H SODR2 : 000025H () R/W - X : : : : bit 15 (SSR) bit 8 bit 7 SODR0 to SODR2 bit 0 Initial value X X X X X X X X B (W)
Access Readable and writable Unused Indeterminate
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MB91F109
(2) Block diagram
Control signals Receive interrupt (to CPU) SC (clock) Transmit clock From U-TIMER Clock select circuit From external clock SC Receive control circuit Transmit control circuit Receive clock Transmit interrupt (to CPU)
SI (receive data)
Start bit detect circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity counter
Transmit parity counter
SO (transmit data)
Receive status judge circuit
Receive shifter
Transmit shifter
Receive error generate signal for DMA (to DMAC)
Receive complete
Serial input data register SIDR
Transmit start
Serial output data register SIDR
R-bus
MD1 MD0
Serial register (SMR) Serial control register (SCR)
CS0 SCKE SOE
PEN P SBL CL A/D REC RXE TXE
Serial status register (SSR)
PE ORE FRE RDRF TDRE RIE TIE
Control signals
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MB91F109
4. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91F109 has 3 channel U-TIMER embedded on the chip. When used as an interval timer, two couple of U-TIMER (ch0, ch1) can be cascaded and an interval of up to 232 x can be counted. (1) Register configuration * U-TIMER register ch.0 to ch.2
Address UTIM0 : 00000078H UTIM1 : 0000007CH UTIM2 : 00000080H bit 15 UTIM0 to UTIM2 bit 0 Initial value 00000000 00000000
B B
(R)
* U-TIMER reload register ch.0 to ch.2
Address UTIMR0 : 00000078H UTIMR1 : 0000007CH UTIMR2 : 00000080H bit 15 UTIMR0 to UTIMR2 bit 0 Initial value 00000000 00000000
B B
(W)
* U-TIMER control register ch.0 to ch.2
Address UTIMC0 : 0000007BH UTIMC1 : 0000007FH UTIMC2 : 00000083H bit 15 (Vacancy) bit 8 bit 7 UTIMC0 to UTIMC2 bit 0 Initial value 0- - 00001
B
(R/W)
( ) : Access R/W : Readable and writable - : Unused
(2)
Block diagram
bit 15 Reload register (U-TIMER)
bit 0
Load bit 15 U-TIMER register (UTIM) Underflow (Peripheral clock) MUX (ch.0 only) Underflow U-TIMER f.f. To UART Clock
U-TIMER control register (UTIMC)
bit 0
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MB91F109
5. PWM Timer
The PWM timer can output high accurate PWM waves efficiently. MB91F109 has inner 4-channel PWM timers, and has the following features. * Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit compare resister with a buffer for duty setting, and a pin controller. * The count clock of a 16-bit down counter can be selected from the following four inner clocks. Inner clock , /4, /16, /64 * The counter value can be initialized "FFFFH" by the resetting or the counter borrow. * PWM output (each channel)
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MB91F109
(1) Register configuration * Control status register H0 to 3
Address PCNH0 : 0000E6H PCNH1 : 0000EEH PCNH2 : 0000F6H PCNH3 : 0000FEH bit 15 bit 8 bit 7 (PCNL) bit 0 Initial value 0000000B
PCNH0 to PCNH3
(R/W)
* Control status register L0 to 3
Address PCNL0 : 0000E7H PCNL1 : 0000EFH PCNL2 : 0000F7H PCNL3 : 0000FFH bit 15 (PCNH) PCNL0 to PCNL3 bit 0 Initial value 00000000
B
(R/W)
* PWM cycle setting register 0 to 3
Address PCSR0 : 0000E2H PCSR1 : 0000EAH PCSR2 : 0000F2H PCSR3 : 0000FAH bit 15 PCSR0 to PCSR3 bit 0 Initial value XXXXXXXXB (W) XXXXXXXXB
* PWM duty setting register 0 to 3
Address PDUT0 : 0000E4H PDUT1 : 0000ECH PDUT2 : 0000F4H PDUT3 : 0000FCH bit 15 PDUT0 to PDUT3 bit 0 Initial value XXXXXXXXB (W) XXXXXXXXB
* PWM timer register 0 to 3
Address PTMR0 : 0000E0H PTMR1 : 0000E8H PTMR2 : 0000F0H PTMR3 : 0000F8H bit 15 PTMR0 to PTMR3 bit 0 Initial value 11111111 11111111
B B
(R)
* General control register 1, 2
Address GCN1 : 0000DCH bit 15 GCN1 bit 0 Initial value 00110010 00010000
B B
(R/W)
Address GCN1 : 0000DFH
bit 15 (Vacancy)
bit 8 bit 7 GCN2
bit 0
Initial value 00000000
B
(R/W)
() R/W R W - X
: : : : : :
Access Readable and writable Read only Write only Unused Indeterminate
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MB91F109
(2) Block diagram * Block diagram (general construction)
16-bit reload timer ch.0
TRG input PWM timer ch.0
PWM0
16-bit reload timer ch.1
General control register 1 (cause selection) 4
TRG input PWM timer ch.1
PWM1
General control register 2
TRG input PWM timer ch.2
PWM2
External TRG0 to TRG3
4
TRG input PWM timer ch.3
PWM3
* Block diagram (for one channel)
PWM cycle setting register (PCSR) Prescaler 1/1 1/4 1 / 16 1 / 64
PWM duty setting register (PDUT)
ck
Load 16-bit down counter Start Borrow
cmp
PPG mask S Peripheral clock R Q
PWM output
Reverse bit Interrupt selection Enable TRG input Edge detect Soft trigger
IRQ
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MB91F109
6. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock). The DMA transfer can be started by the interruption. The MB91F109 consists of 3 channels of the 16-bit reload timer. (1) Register configuration * 16-bit reload timer control status register 0 to 2
Address TMCSR0 : 00002EH TMCSR1 : 000036H TMCSR2 : 000042H bit 15 TMCSR0 to TMCSR2 bit 0 Initial value - - - - 0000 00000000
B B
(R/W)
* 16-bit timer register 0 to 2
Address TMR0 : 00002AH TMR1 : 000032H TMR2 : 00003EH bit 15 TMR0 to TMR2 bit 0 Initial value XXXXXXXXB (R) XXXXXXXXB
* 16-bit reload register 0 to 2
Address TMRLR0 : 000028H TMRLR1 : 000030H TMRLR2 : 00003CH bit 15 TMRLR0 to TMRLR2 bit 0 Initial value XXXXXXXXB (W) XXXXXXXXB
() R/W R W - X
: : : : : :
Access Readable and writable Read Only Write Only Unused Indeterminate
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MB91F109
(2) Block diagram
16 16-bit reload register (TMRLR) 8 Reload RELD 16 16-bit down counter UF OUTE OUTL 2 GATE R-bus CSL1 Clock selector CSL0 2
Retrigger
OUT CTL.
INTE 2 UF CNTE TRG IRQ
IN CTL.
EXCK 21 23 25 3 Prescaler clear
MOD2 MOD1
PWM (ch.0, ch.1) A/D (ch.2)
Internal clock
MOD0
3
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MB91F109
7. Bit Search Module
The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. (1) Register configuration * Bit search module 0, 1-detection data register
Address BSD0 : 000003F0H BSD1 : 000003F4H bit 31 BSD0, BSD1 bit 0 Initial value XXXXXXXXB X X X X X X X X B (R/W) XXXXXXXXB XXXXXXXXB
* Bit search module transition-detection data register
Address 000003F8H bit 31 BSDC bit 0 Initial value XXXXXXXXB X X X X X X X X B (W) XXXXXXXXB XXXXXXXXB
* Bit search module detection result register
Address 000003FCH bit 31 BSRR bit 0 Initial value XXXXXXXXB X X X X X X X X B (R) XXXXXXXXB XXXXXXXXB
() R/W R W X
: : : : :
Access Readable and writable Read only Write only Indeterminate
(2) Block diagram
Input latch
Address decoder
Detection mode
D-bus
Single-detection data recovery
Bit search circuit
Bit search module detection result register (BSRR)
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MB91F109
8. 10-bit A/D Converter (Successive Approximation Conversion Type)
The A/D converter is the module which converts an analog input voltage to a digital value, and it has following features. * * * * Minimum converting time: 5.6 s/ch. (system clock: 25 MHz) Inner sample and hold circuit Resolution: 10 bits Analog input can be selected from 4 channels by program. Single convert mode: 1 channel is selected and converted. Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable. Continuous convert mode: Converting the specified channel repeatedly. Stop convert mode: After converting one channel then stop and wait till next activation synchronizing at the beginning of conversion can be performed. * DMA transfer operation is available by interruption. * Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reload timer (rising edge).
(1) Register configuration * A/D converter control status register
Address 0000003AH bit 15 ADCS bit 0 Initial value 00000000 00000000
B B
(R/W)
* A/D converter data register
Address 00000038H bit 15 ADCR bit 0 Initial value 0 0 0 0 0 0 XXB (R) XXXXXXXXB
() R/W R X
: : : :
Access Readable and writable Read only Indeterminate
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MB91F109
(2) Block diagram
AVCC
AVRH
AVSS
Internal voltage generator MPX
AN0 Input circuit AN1 AN2 AN3 R-bus Decoder A/D Converter Data register (ADCR) A/D Converter control status register (ADCS) Trigger start ATG TIM0 (internal connection) (16-bit reload timer 2) (Peripheral clock) Timer start Operating clock Prescaler Sample & hold circuit Successive approximation register Comparator
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MB91F109
9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts. * Hardware Configuration Interrupt controller is configured by ICR resistor, interrupt priority decision circuit, interrupt level, vector generation and HLDREQ cancel request, and has the following functions. * Main Functions NMI request/Interrupt request detection Priority (judgement) decision (via level and vector) Transfer of judged interrupt level to CPU Transfer of judged interrupt vector to CPU Return instruction from the stop mode via NMI/interrupt Generation of HOLD request cancel request to the bus timer
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MB91F109
(1) Register configuration * Interrupt control register 0 to 31, 47
Address 00000400H 00000401H 00000402H 00000403H 00000404H 00000405H 00000406H 00000407H 00000408H 00000409H 0000040AH 0000040BH 0000040CH 0000040DH 0000040EH 0000040FH 00000410H bit 7 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 bit 0 Initial value - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) Address 00000411H 00000412H 00000413H 00000414H 00000415H 00000416H 00000417H 00000418H 00000419H 0000041AH 0000041BH 0000041CH 0000041DH 0000041EH 0000041FH 0000042FH bit 7 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR47 bit 0 Initial value - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W)
* Hold request cancel request level setting register
Address 00000431H bit 7 HRCL bit 0 Initial value - - - 11111
B
(R/W)
( ) : Access R/W : Readable and writable - : Unused
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MB91F109
(2) Block diagram
INT0*2
OR NMI NMI processing 4 Level judgment ICR00
Priority judgment 5 5 LEVEL4 to LEVEL0*4
RI00 * * * RI47 (DLYIRQ) * * *
Level, vector generation
HLDREQ cancel request
HLDCAN*3
6 * * ICR47 Vector judgment
6
VCT5 to VCT0*5
DLYI*1
R-bus
*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section "11. Delayed Interrupt Module" for detail). *2: INT0 is a wake-up signal to clock control block in the sleep or stop status. *3: HLDCAN is a bus release request signal for bus masters other than CPU. *4: LEVEL4 to LEVEL0 are interrupt level outputs. *5: VCT5 to VCT0 are interrupt vector outputs.
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MB91F109
10. External Interrupt/NMI Control Block
The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to INT3 pins. Detecting levels can be selected from "H", "L", rising edge and falling edge (not for NMI pin). (1) Register configuration * Interrupt enable register
Address 00000095H bit 15 (EIRR) bit 7 ENIR bit 0 Initial value 00000000
B
(R/W)
* External interrupt cause register
Address 00000094H bit 15 EIRR bit 8 (ENIR) bit 0 Initial value 00000000
B
(R/W)
* External interrupt request level setting register
Address 00000099H bit 15 ELVR bit 0 Initial value 00000000
B
(R/W)
( ) : Access R/W : Readable and writable
(2) Block diagram
8 Interrupt enable register (ENIR) 9 R-bus 5
Interrupt request
Gate
Cause F/F
Edge detection circuit
INT0 to INT3 NMI
8
External interrupt cause register (EIRR)
8
External interrupt request level setting register (ELVR)
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MB91F109
11. Delayed Interrupt Module
Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed interrupt module, an interrupt request to CPU can be generated/cancelled by the software. Refer to the section "9. Interrupt Controller" for delayed interrupt module block diagram. * Register configuration * Delayed interrupt control register
Address 00000430H bit 7 DICR bit 0 Initial value -------0
B
(R/W)
( ) : Access R/W : Readable and writable - : Unused
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MB91F109
12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions. * * * * * * CPU clock generation (including gear function) Peripheral clock generation (including gear function) Reset generation and cause hold Standby function DMA request prohibit PLL (multiplier circuit) embedded
(1) Register configuration * Reset cause register/watchdog cycle control register
Address 00000480H bit 15 RSRR bit 10 bit 9 bit 8 WTCR (STCR) bit 0 Initial value 1 XXXX- 0 0
B
(R/W)
* Standby control register
Address 00000481H bit 15 (RSRR/WTCR) bit 7 STCR bit 0 Initial value 000111- B
(R/W)
* DMA controller request squelch register
Address 00000482H bit 15 PDRR bit 8 (CTBR) bit 0 Initial value - - - - 0000
B
(R/W)
* Timebase timer clear register
Address 00000483H bit 15 (PDRR) bit 7 CTBR bit 0 Initial value X X X X X X X X B (W)
* Gear control register
Address 00000484H bit 15 GCR bit 8 (WPR) bit 0 Initial value 110011- 1
B
(R/W)
* Watchdog reset occurrence postpone register
Address 00000485H bit 15 (GCR) bit 7 WPR bit 0 Initial value X X X X X X X X B (W)
* PLL control register
Address 00000488H bit 15 PCTR bit 8 (Vacancy) bit 0 Initial value 00- - 0- - B
(R/W)
() R/W R W - X
: : : : : :
Access Readable and writable Read Only Write Only Unused Indeterminate
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MB91F109
(2) Block diagram
[Gear control block]
Gear control register (GCR)
CPU gear R-bus
PLL control register (PCTR)
Peripheral gear CPU clock Internal bus clock External bus clock Peripheral DMA clock Internal peripheral clock
X0 X1
Oscillator circuit
PLL 1/2
Selection circuit
Internal clock generation circuit
[Stop/sleep control block] Internal interrupt request Internal reset Standby control register (STCR) STOP state CPU hold enable Status transition control circuit
Reset generation F/F
SLEEP state CPU hold request Internal reset
[DMA prohibit circuit] DMA request
DMA request prohibit register (PDRR)
[Reset cause circuit] Power on cell RST pin
Reset cause register (RSRR) [Watchdog control block] Watchdog reset generation postpone register (WPR) Watchdog reset postpone register F/F Timebase timer clear register (CTBR) Timebase time Count clock
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MB91F109
13. External Bus Interface
The external bus interface controls the interface between the device and the external memory and also the external I/O, and has the following features. * 25-bit (32 Mbytes) address output * 6 independent banks owing to the chip select function. Can be set to anywhere on the logical address space for minimum unit 64 Kbytes. Total 32 Mbytes x 6 area setting is available by the address pin and the chip select pin. * 8/16-bit bus width setting are available for every chip select area. * Programmable automatic memory wait (max. for 7 cycles) can be inserted. * DRAM interface support Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F) Single CAS DRAM Hyper DRAM 2 banks independent control (RAS, CAS, etc. control signals) DRAM select is available from 2CAS/1WE and 1CAS/2WE. Hi-speed page mode supported CBR/self refresh supported Programmable wave form * Unused address/data pin can be used for I/O port. * Little endian mode supported * Without Clock doubler: Internal bus 25 MHz, external bus 25 MHz (at source oscillation 12.5 MHz)
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MB91F109
(1) Register configuration * Area select register 1 to 5
Address 0000060CH 00000610H 00000614H 00000618H 0000061CH bit 15 ASR1 ASR2 ASR3 ASR4 ASR5 bit 0 Initial value 00000000 00000001 0 0 0 0 0 0 0 0 bit 0 AMR1 to AMR5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1
B B B B B B B B B B
(W)
* Area mask register 1 to 5
Address bit 15 AMR1 : 0000060EH AMR2 : 00000612H AMR3 : 00000616H AMR4 : 0000061AH AMR5 : 0000061EH Initial value 00000000 00000000
B B
(W)
* Area mode register 0, 1, 32, 4, 5
Address AMD0 : 00000620H AMD1 : 00000621H AMD32 : 00000622H AMD4 : 00000623H AMD5 : 00000624H bit 15 AMD0 AMD32 AMD5 bit 8 bit 7 AMD1 AMD4 (DSCR) bit 0
Initial value - - - 00111 0- - 00000 00000000 0- - 00000 0- - 00000
B B B B
(R/W) (R/W) (R/W)
B
* DRAM single control register
Address 00000625H bit 15 (AMD5) bit 8 bit 7 DSCR bit 0 Initial value 00000000
B
(W)
* Refresh control register
Address 00000626H bit 15 RFCR bit 0 Initial value - - XXXXXXB (R/W) 00- - - 000B Initial value - - - - 1100 - 1111111 -------1 11111111 Initial value 00000000 0000000-
* External pin control register 0, 1
Address EPCR0: 00000628H EPCR1: 0000062AH bit 15 EPCR0 EPCR1 bit 0
B B B B
(W) (W)
* DRAM control register 4, 5
Address DMCR4: 0000062CH DMCR5: 0000062EH bit 15 DMCR4, DMCR5 bit 0
B B
(R/W)
* Litter endian register
Address 000007FEH bit 15 LER bit 8 bit 7 (MODR) bit 0 Initial value - - - - - 000
B
(W)
* Mode register
Address 000007FFH () R/W W - X : : : : : Access Readable and writable Write only Unused Indeterminate bit 15 (LER) bit 8 bit 7 MODR bit 0 Initial value X X X X X X X X B (W)
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MB91F109
(2) Block diagram
Address bus 32
Data bus 32
A-OUT External data bus Write buffer Switch MUX
Read buffer
Switch
DATA BLOCK ADDRESS BLOCK
+1 or +2 External address bus Inpage Address buffer Shifter 6 Comparator
Area select register(ASR) Area mask register(AMR)
CS0 to CS5
DRAM control
DRAM control register (DMCR)
8
RAS0, RAS1 CS0L, CS1L CS0H, CS1H DW0, DW1
Underflow
Refresh counter register (RFCR)
To TBT 3
External pin control block All blocks control Registers and control
RD WR0, WR1 BRQ BGRNT CLK RDY
4
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MB91F109
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter Power supply voltage Analog supply voltage Analog reference voltage Analog pin input voltage Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level maximum total output current "L" level average total output current "H" level maximum output current "H" level average output current "H" level maximum total output current "H" level average total output current Power consumption Operating temperature Storage temperature *1: *2: *3: *4: *5: Symbol VCC AVCC AVRH VIA VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- 0 -55 Max. VSS + 4.0 VSS + 4.0 VSS + 4.0 AVCC + 0.3 VCC + 0.3 VCC + 0.3 10 8 100 50 -10 -4 -50 -20 500 +70 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mW C C *5 *5 *3 *4 *3 *4 *1 *2 *2 Remarks
VCC must not be less than VSS - 0.3 V. Make sure that the voltage does not exceed VCC + 0.3 V, such as when turning on the device. Maximum output current is a peak current value measured at a corresponding pin. Average output current is an average current for a 100 ms period at a corresponding pin. Average total output current is an average current for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB91F109
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol VCC Power supply voltage Analog supply voltage Analog reference voltage Operating temperature VCC AVCC AVRH TA Value Min. 3.15 3.15 VSS - 0.3 AVSS 0 Max. 3.6 3.6 VSS + 3.6 AVCC +70 Unit V V V V C Remarks Normal operation Retaining the RAM state in stop mode
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MB91F109
* Normal operation warranty rage
(V)
Normal operation warranty range (TA = 0C to +70C) Net masked area are fCPP . Supply voltage VCC
3.6
3.0 25
Internal clock fCP/fCPP
(MHz)
0
0.625
* External/Internal clock setting rage
Max. internal clock frequency setting fCP/fCPP
(MHz) 25
PLL system (12.5MHz(Fixed) 2 multiplication) Peripheral
fCPP
fCP 12.5
Divide-by-2 system
5
0
0
10 12.5
25
FC (MHz)
External clock Self-oscillation Notes: * When using PLL, the external clock must be used need 12.5 MHz. * PLL oscillation stabilizing period > 100 s * The setting of internal clock must be within above ranges.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB91F109
3. DC Characteristics
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name Input pin except for hysteresis input NMI, RST, P40 to P47, P50 to P57, P60 to P67, P70, P81, P83 to P85, PA0 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7 Input other than following symbols NMI, RST, P40 to P47, P50 to P57, P60 to P67, P70, P81, P83 to P85, PA0 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 P80 to P85 PA0 to PA6 PB0 to PB7 PE0 to PE7 PF0 to PF7 RST VCC VCC VCC Except for VCC, AVCC, AVSS, VSS Condition Value Min. 0.65 x VCC Typ. -- Max. VCC + 0.3 Unit Remarks
VIH
--
V
"H" level input voltage VIHS
--
0.8 x VCC
--
VCC + 0.3
V
Hysteresis input
VIL
--
VSS - 0.3
--
0.25 x VCC
V
"L" level input voltage VILS
--
VSS - 0.3
--
0.2 x VCC
V
Hysteresis input
"H" level output VOH voltage "L" level output voltage
VCC = 3.15 V IOH = -4.0 mA VCC = 3.15 V IOL = 4.0 mA VCC = 3.6 V 0.45 V < VI < VCC VCC = 3.6 V VI = 0.45 V FC = 12.5 MHz VCC = 3.3 V FC = 12.5 MHz VCC = 3.3 V TA = +25C VCC = 3.3 V --
VCC - 0.5
--
--
V
VOL
--
--
0.4
V
Input leakage current ILI (Hi-Z output leakage current) Pull-up resistance RPULL ICC Power supply current ICCS ICCH Input capacitance 66 CIN
-5
--
+5
A
25 -- -- -- --
50 75 35 1.4 10
100 100 50 150 --
k
(2 multiplication)
mA Operation at 25 MHz mA Sleep mode A Stop mode pF
MB91F109
4. FLASH Memory Programming/Erasing Characteristics
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Condition Value Min. -- Typ. 1.5 Max. 13.5 Unit Remarks Except for the write time before internal erase operation Except for the write time before internal erase operation Except for the over head time of the system Except for the over head time of the system
Sector erasing time
s
Chip erasing time Byte programming time Chip programming time Erase/Program cycle
TA = +25C VCC = 3.3 V
-- -- --
-- 16 2.1 --
27.0 -- -- --
s s s cycle
--
100
Note: The internal automatic algorithm continues operations for up to 48 ms, for each 1-byte writing operation.
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MB91F109
5. AC Characteristics
(1) Measurement Conditions (VCC = 3.15 V to 3.6 V) Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Symbol VIH VIL VOH VOL Value Min. -- -- -- -- Typ. 1/2* x VCC 1/2* x VCC 1/2* x VCC 1/2* x VCC Max. -- -- -- -- Unit V V V V Remarks
*: Input rise/fall time is 10 ns. and less.
VCC
Input VIH
Output VOH VOL
0.0 V
VIL
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MB91F109
(2) Clock Timing Rating (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name Condition Self-oscillation at 12.5 MHz Internal operation at 25 MHz (Via PLL, double) Self-oscillation (divide-by-2 input) External clock (divide-by-2 input) Self-oscillation at 12.5 MHz Internal operation at 25 MHz (Via PLL, double) -- Self-oscillation at 12.5 MHz Internal operation at 25 MHz (Via PLL, double) 12.5 MHz to 25.0 MHz 12.5 MHz and less -- CPU system Peripheral system CPU system Peripheral system Value Min. Max. Unit Remarks
FC Clock frequency FC FC
X0, X1
12.5
12.5
MHz
X0, X1 X0, X1
10 10
25 25
MHz MHz
Clock cycle time
tC
X0, X1
--
80
ns
tC Frequency shift ratio (when locked)
X0, X1
40
100
ns
f
--
--
5
%
*1
PWH, PWL Input clock pulse width PWH Input clock rising/falling time Internal operating clock frequency Internal operating clock cycle time tCR, tCF fCP fCPP tCP tCPP
X0, X1
18.5
--
ns
Input clock pulse to X0 and X1 Input clock pulse to X0 only (tCR + tCF)
X0 X0, X1 -- -- -- --
25 -- 0.625*2 0.625* 40 40
2
-- 8 25 25 1600*2 1600*2
ns ns MHz MHz ns ns
*1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system.
+ + Center frequency f0 - -
f =
x100 (%) f0
*2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and a 1/8 gear.
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MB91F109
* Load conditions
Output pin C = 50 pF
* Clock timing rating measurement conditions
tC 0.8 VCC 0.8 VCC 0.2 VCC PWH tCF PWL tCR 0.8 VCC 0.2 VCC
X0
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MB91F109
(3) Clock Output Timing (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Cycle time CLK CLK CLK CLK Symbol Pin name tCYC tCHCL tCLCH CLK CLK CLK Condition -- -- Value Min. tCP*1 1/2 x tCYC - 5 1/2 x tCYC - 5 Max. -- 1/2 x tCYC + 5 1/2 x tCYC + 5 Unit ns ns ns Remarks *2 *3 *4
*1: For information on tCP (internal operating clock cycle time), see "(2) Clock Timing Rating." *2: tCYC is a frequency for 1 clock cycle including a gear cycle. *3: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8, respectively. Min. : (1 - n/2) x tCYC - 10 Max. : (1 - n/2) x tCYC + 10 *4: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8, respectively. Min. : n/2 x tCYC - 10 Max. : n/2 x tCYC + 10
tCYC tCHCL CLK VOH VOL tCLCH VOH
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MB91F109
The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows: However, in this chart source oscillation input means X0 input clock.
Source oscillation input (when using the doubler) (1) PLL system (CHC bit of GCR set to "0") (a) Gear x 1 CLK pin CCK1/0: "00" tCYC
Source oscillation input (2) 2 dividing system (CHC bit of GCR set to "1") (a) Gear x 1 CLK pin CCK1/0: "00" tCYC
(b) Gear x 1/2 CLK pin CCK1/0: "01" (c) Gear x 1/4 CLK pin CCK1/0: "10" (d) Gear x 1/8 CLK pin CCK1/0: "11"
tCYC
tCYC
tCYC
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MB91F109
* Ceramic oscillator applications
Recommended circuit (2 contacts)
Recommended circuit (3 contacts)
X0 *
X1
X0 *
X1
C1
C2
C1
C2
C1, C2 internally connected.
*: Murata Mfg. Co., Ltd.
* Discreet type Oscillation frequency [MHz] CSA 5.00 to 6.30 CST CSA CST CSA 6.31 to 10.0 CST CSA CST CSA 10.1 to 13.0 CST CSA CST 13.01 to 15.00 CSA CST Model MG MGW MG093 MGW093 MTZ MTW MTZ093 MTW093 MTZ MTW MTZ093 MTW093 MXZ040 MXW0C3 Load capacitance C1 = C2 [pF] 30 (30) 30 (30) 30 (30) 30 (30) 30 (30) 30 (30) 15 (15) Power supply voltage VCC [V] 3.15 to 3.6
3.15 to 3.6
3.15 to 3.6
3.15 to 3.6
3.15 to 3.6
3.15 to 3.6
3.2 to 3.6
( ): C1 and C2 internally connected 3 contacts type.
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MB91F109
(4) Reset Input Ratings (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Reset input time Symbol Pin name Condition tRSTL RST -- Value Min. tCP* x 5 Max. -- Unit ns Remarks
*: For information on tCP (internal operating clock cycle time), see "(2) Clock Timing Rating."
tRSTL RST 0.2 VCC 0.2 VCC
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MB91F109
(5) Power on Supply Specifications (Power-on Reset) (AVCC = VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name Condition Value Min. -- Max. 18 Unit Remarks VCC < 0.2 V before the power supply rising Repeated operations
Power supply rising time
tR
VCC
VCC = 3.3 V
ms
Power supply shut off time Oscillation stabilizing time
tOFF tOSC
VCC -- --
1 2 x tC* x 220 + 100 s
-- --
ms ns
*: For information on tC (clock cycle time), see "(2) Clock Timing Rating."
tR 0.9 VCC VCC 0.2 V 0.2 V tOFF Note: Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage. 0.2 V
VCC A voltage rising rate of 50 mV/ms or less is recommended. VSS
336 ms approx. (@12.5 MHz) VCC (Oscillation stabilizing time)
tOSC 0.8 VCC
RST
tRSTL + (tC x 219) tRSTL: Reset input time
Notes: * Set RST pin to "L" level when turning on the device, at least the described above duration after the supply voltage reaches Vcc is necessary before turning the RST to "H" level. * Some internal resistors which are initialized only via power on reset are embedded in the device. To initialize these resistors, run power on reset by returning on the power supply.
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MB91F109
(6) Normal Bus Access Read/write Operation (AVCC = VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol tCHCSL CS0 to CS5 delay time tCHCSH Address delay time Data delay time RD delay time tCHAV tCHDV tCLRL tCLRH tCLWL WR0, WR1 delay time tCLWH Valid address valid data input time tAVDV Pin name CLK, CS0 to CS5 CLK, CS0 to CS5 CLK, A24 to A00 CLK, D31 to D16 CLK, RD CLK, RD CLK, WR0, WR1 CLK, WR0, WR1 A24 to A00, D31 to D16 RD, D31 to D16 RD, D31 to D16 RD, D31 to D16 -- Condition Value Min. -- -- -- -- -- -- -- -- -- -- 10 10 Max. 15 15 15 15 15 15 15 15 3/2 x tCYC*1 - 25 tCYC*1 - 10 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns *2 *3 *2 Remarks
RD valid data input time tRLDV Data set up RD time RD data hold time tDSRH tRHDX
*1: For information on tCYC (a cycle time of peripheral system clock), see "(3) Clock Output Timing." *2: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC x extended cycle number for delay) to this rating. *3: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (2 - n/2) x tCYC - 25
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MB91F109
BA1 tCYC CLK 2.4 V 0.8 V 2.4 V
BA2
0.8 V
2.4 V
tCHCSL CS0 to CS5 0.8 V
tCHCSH 2.4 V
tCHAV A24 to A00 2.4 V 0.8 V 2.4 V 0.8 V
tCLRL RD 0.8 V tRLDV
tCLRH 2.4 V
tRHDX tAVDV D31 to D16 2.4 V 0.8 V Read 2.4 V 0.8 V tDSRH tCLWL WR0, WR1 0.8 V 2.4 V tCLWH tCHDV D31 to D16 2.4 V 0.8 V Write 2.4 V 0.8 V
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MB91F109
(7) Ready Input Timing (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name RDY, CLK CLK, RDY Condition -- Value Min. 15 0 Max. -- -- Unit ns ns Remarks
RDY set up time CLK tRDYS CLK RDY hold time tRDYH
tCYC CLK 2.4 V 2.4 V tRDYH
0.8 V tRDYS
0.8 V tRDYS tRDYH
RDY When wait(s) is inserted.
2.4 V 0.8 V
0.8 V
2.4 V
RDY When no wait is inserted.
2.4 V
2.4 V
0.8 V
0.8 V
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MB91F109
(8) Hold Timing (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name Condition tCHBGL BGRNT delay time tCHBGH Pin floating BGRNT time BGRNT pin valid time tXHAL tHAHV CLK, BGRNT CLK, BGRNT BGRNT BGRNT -- Value Min. -- -- Max. 6 6 Unit ns ns ns ns Remarks
tCYC* - 10 tCYC* + 10 tCYC* - 10 tCYC* + 10
*: For information on tCYC (a cycle time of peripheral system clock), see "(3) Clock Output Timing." Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change.
tCYC CLK 2.4 V 2.4 V 2.4 V 2.4 V
BRQ
tCHBGL BGRNT 0.8 V tXHAL Each pin High impedance
tCHBGH 2.4 V
tHAHV
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MB91F109
(9) Normal DRAM Mode Read/Write Cycle (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time Symbol tCLRAH tCHRAL tCLCASL CAS delay time tCLCASH ROW address delay time COLUMN address delay time DW delay time Output data delay time RAS valid data input time CAS valid data input time CAS data hold time tCHRAV tCHCAV tCHDWL tCHDWH tCHDV1 tRLDV tCLDV Pin name CLK, RAS CLK, RAS CLK, CS0H, CS1H, CS0L, CS1L CLK, CS0H, CS1H, CS0L, CS1L CLK, A24 to A00 CLK, A24 to A00 CLK, DW*2 CLK, DW*2 CLK, D31 to D16 RAS, D31 to D16 CS0H, CS1H, CS0L, CS1L, D31 to D16 CS0H, CS1H, CS0L, CS1L, D31 to D16 Condition Value Min. -- -- -- Max. 15 15 15 Unit ns ns ns Remarks
-- -- -- -- -- -- -- -- --
15 15 15 15 15 15 5/2 x tCYC*1 - 16 tCYC*1 - 17
ns ns ns ns ns ns ns ns *3 *4 *3
tCADH
10
--
ns
*1: For information on tCYC (a cycle time of peripheral system clock), see "(3) Clock Output Timing." *2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE. *3: When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating. *4: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (3 - n/2) x tCYC - 16
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MB91F109
Q1 tCYC CLK 2.4 V 0.8 V
Q2
Q3
Q4
Q5
2.4 V
2.4 V
2.4 V
0.8 V
0.8 V
2.4 V
RAS tCLRAH CS0H, CS1H, CS0L, CS1L
2.4 V
0.8 V tCHRAL tCLCASL 0.8 V tCLCASH 2.4 V
tCHRAV A24 to A00 2.4 V 0.8 V ROW address 2.4 V 0.8 V
tCHCAV 2.4 V 0.8 V tRLDV tCLDV tCADH Read 2.4 V 0.8 V
COLUMN address 2.4 V
0.8 V
D31 to D16
2.4 V 0.8 V
DW
2.4 V 0.8 V tCHDWL tCHDWH
D31 to D16
2.4 V 0.8 V tCHDV1
Write
2.4 V 0.8 V
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MB91F109
(10) Normal DRAM Mode Fast Page Read/Write Cycle (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time Symbol tCLRAH tCLCASL CAS delay time tCLCASH COLUMN address delay time DW delay time Output data delay time CAS valid data input time CAS data hold time tCHCAV tCHDWH tCHDV1 tCLDV Pin name CLK, RAS CLK, CS0H, CS1H, CS0L, CS1L CLK, CS0H, CS1H, CS0L, CS1L CLK, A24 to A00 CLK, DW*2 CLK, D31 to D16 CS0H, CS1H, CS0L, CS1L, D31 to D16 CS0H, CS1H, CS0L, CS1L, D31 to D16 Condition Value Min. -- -- Max. 15 15 Unit ns ns Remarks
-- -- -- -- -- --
15 15 15 15 tCYC*1 - 17
ns ns ns ns ns *3
tCADH
10
--
ns
*1: For information on tCYC (a cycle time of peripheral system clock), see "(3) Clock Output Timing." *2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE. *3: When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
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MB91F109
Q5 CLK
Q4 2.4 V 0.8 V
Q5 0.8 V
Q4
Q5 2.4 V 0.8 V
tCLRAH RAS 2.4 V
tCLCASL CS0H, CS1H, CS0L, CS1L
tCLCASH 2.4 V
0.8 V
tCHCAV COLUMN address 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V
A24 to A00
COLUMN address
COLUMN address
tCLDV 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V
tCADH 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V
D31 to D16
Read
Read
Read
tCHDWH DW 2.4 V
tCHDV1 D31 to D16 2.4 V 0.8 V Write 2.4 V 0.8 V 2.4 V 0.8 V Write 2.4 V 0.8 V
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MB91F109
(11) Single DRAM Timing (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time Symbol tCLRAH2 tCHRAL2 tCHCASL2 CAS delay time tCHCASH2 ROW address delay time COLUMN address delay time DW delay time Output data delay time CAS Valid data input time CAS data hold time tCHRAV2 tCHCAV2 tCHDWL2 tCHDWH2 tCHDV2 tCLDV2 Pin name CLK, RAS CLK, RAS CLK, CS0H, CS1H, CS0L, CS1L CLK, CS0H, CS1H, CS0L, CS1L CLK, A24 to A00 CLK, A24 to A00 CLK, DW*2 CLK, DW*2 CLK, D31 to D16 CS0H, CS1H, CS0L, CS1L, D31 to D16 CS0H, CS1H, CS0L, CS1L, D31 to D16 -- -- Condition Value Min. -- Max. 15 15 n/2 x tCYC*1 Unit ns ns ns Remarks
-- -- -- -- -- -- --
15 15 15 15 15 15 (1 - n/2) x tCYC*1 - 17 --
ns ns ns ns ns ns ns
tCADH2
10
ns
*1: For information on tCYC (a cycle time of peripheral system clock), see "(3) Clock Output Timing." *2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE.
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MB91F109
tCYC Q1 CLK 2.4 V 0.8 V Q2 2.4 V Q3 2.4 V
*1 Q4S 2.4 V
Q4S 2.4 V
Q4S 2.4 V
RAS
2.4 V tCLRAH2
0.8 V tCHRAL2 tCHCASL2
CS0H, CS1H, CS0L, CS1L
tCHCASH2 0.8 V 2.4 V 0.8 V 2.4 V
A24 to A00
2.4 V 0.8 V
ROW address
2.4 V 0.8 V
2.4 V COLUMN-0 0.8 V
COLUMN-1
COLUMN-2
tCHRAV2
tCHCAV2 tCADH2 tCLDV2
2.4 V 0.8 V 2.4 V 0.8 V
D31 to D16 (Read)
Read-0
Read-1
Read-2
DW (Read)
0.8 V tCHDWL2
2.4 V tCHDWH2
*2 D31 to D16 (Write) 2.4 V 0.8 V tCHDV2 Write-0 2.4 V 0.8 V tCHDV2 2.4 V 0.8 V 2.4 V 2.4 V 0.8 V 0.8 V Write-1 Write-2
*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. *2: indicates the timing when the bus cycle begins from the high speed page mode.
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MB91F109
(12) Hyper DRAM Timing (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time Symbol tCLRAH3 tCHRAL3 tCHCASL3 CAS delay time tCHCASH3 ROW address delay time COLUMN address delay time RD delay time tCHRAV3 tCHCAV3 tCHRL3 tCHRH3 tCLRL3 DW delay time Output data delay time CAS valid data input time CAS data hold time tCHDWL3 tCHDWH3 tCHDV3 tCLDV3 Pin name CLK, RAS CLK, RAS CLK, CS0H, CS1H, CS0L, CS1L CLK, CS0H, CS1H, CS0L, CS1L CLK, A24 to A00 CLK, A24 to A00 CLK, RD CLK, RD CLK, RD CLK, DW*2 CLK, DW*2 CLK, D31 to D16 CS0H, CS1H, CS0L, CS1L, D31 to D16 CS0H, CS1H, CS0L, CS1L, D31 to D16 -- Condition Value Min. -- -- -- Max. 15 15 n/2 x tCYC*1 Unit ns ns ns Remarks
-- -- -- -- -- -- -- -- -- --
15 15 15 15 15 15 15 15 15 tCYC - 17
ns ns ns ns ns ns ns ns ns ns
tCADH3
10
--
ns
*1: For information on tCYC (a cycle time of peripheral system clock), see "(3) Clock Output Timing." *2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE.
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MB91F109
tCYC Q1 CLK 2.4 V 0.8 V Q2 2.4 V Q3 2.4 V
*1 Q4H 2.4 V 0.8 V Q4H 2.4 V Q4H 2.4 V
RAS
2.4 V tCLRAH3
0.8 V tCHRAL3 tCHCASL3
CS0H, CS1H, CS0L, CS1L
tCHCASH3 2.4 V 0.8 V 0.8 V 2.4 V
A24 to A00
2.4 V 0.8 V
ROW address tCHCAV3
2.4 V 0.8 V
2.4 V COLUMN-0 0.8 V
COLUMN-1
COLUMN-2
tCHRAV3
DW (Read)
0.8 V tCHRL3
*2 0.8 V tCLRL3 tCLDV3
2.4 V tCHRH3 tCADH3 Read-0 Read-1
2.4 V 0.8 V
D31 to D16 (Read)
2.4 V 0.8 V
DW (Read)
0.8 V tCHDWL3
2.4 V tCHDWH3
*2 D31 to D16 (Write) 2.4 V 0.8 V tCHDV3 Write-0 2.4 V 0.8 V tCHDV3 2.4 V 0.8 V Write-1 Write-2
*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. *2: indicates the timing when the bus cycle begins from the high speed page mode.
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MB91F109
(13) CBR Refresh (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time Symbol tCLRAH tCHRAL tCLCASL CAS delay time tCLCASH Pin name CLK, RAS CLK, RAS CLK, CS0H, CS1H, CS0L, CS1L CLK, CS0H, CS1H, CS0L, CS1L -- Condition Value Min. -- -- -- Max. 15 15 15 Unit ns ns ns Remarks
--
15
ns
tCYC R1 CLK 2.4 V 0.8 V
R2 2.4 V 0.8 V
R3 2.4 V
R4 0.8 V
RAS
2.4 V tCLRAH
0.8 V tCHRAL
CS0H, CS1H, CS0L, CS1L
0.8 V tCLCASL
2.4 V tCLCASH
DW
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MB91F109
(14) Self Refresh (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time Symbol tCLRAH tCHRAL tCLCASL CAS delay time tCLCASH Pin name CLK, RAS CLK, RAS CLK, CS0H, CS1H, CS0L, CS1L CLK, CS0H, CS1H, CS0L, CS1L -- Condition Value Min. -- -- -- Max. 15 15 15 Unit ns ns ns Remarks
--
15
ns
tCYC SR1 CLK 2.4 V
SR2 2.4 V 0.8 V
SR3 2.4 V
SR3 0.8 V
tCHRAL RAS
tCLRAH 2.4 V
0.8 V
CS0H, CS1H, CS0L, CS1L
0.8 V tCLCASL
2.4 V tCLCASH
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MB91F109
(15) UART Timing (VCC = 3.15V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Serial clock cycle time Valid SIN SCLK SCLK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width Valid SIN SCLK SCLK valid SIN hold time Symbol Pin name Condition tSCYC tIVSH tSHIX tSHSL tSLSH tIVSH tSHIX -- -- -- -- -- -- -- -- -- External shift clock mode Internal shift clock mode Value Min. 8 x tCYCP* -80 100 60 4 x tCYCP* 4 x tCYCP* -- 60 60 Max. -- 80 -- -- -- -- 150 -- -- Unit ns ns ns ns ns ns ns ns ns Remarks
SCLK SOUT delay time tSLOV
SCLK SOUT delay time tSLOV
*: For information on tCYCP (a cycle time of peripheral system clock), see "(2) Clock Timing Rating." Notes: This rating is for AC characteristics in CLK synchronous mode. * Internal shift clock mode
tSCYC SCLK 2.4 V 0.8 V tSLOV SOUT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 V
* External shift clock mode
tSLSH SCLK 0.2 VCC(0.7V) 0.2 VCC(0.7V) tSLOV SOUT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC tSHSL 0.8 VCC(2.6V) 0.8 VCC(2.6V)
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MB91F109
(16) Trigger System Input Timing (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter A/D start trigger input time Symbol tATGX Pin name ATG Condition -- Value Min. 5 x tCYCP* Max. -- Unit ns Remarks
*: For information on tCYCP (a cycle time of peripheral system clock), see "(2) Clock Timing Rating."
tATGX ATG 0.2 VCC 0.2 VCC
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(17) DMA Controller Timing (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name DREQ0 to DREQ2 CLK, DACK0 to DACK2 CLK, DACK0 to DACK2 CLK, EOP0 to EOP2 CLK, EOP0 to EOP2 CLK, DACK0 to DACK2 CLK, DACK0 to DACK2 CLK, EOP0 to EOP2 CLK, EOP0 to EOP2 -- Condition Value Min. 2 x tCYC* -- -- -- -- -- -- -- -- Max. -- 6 6 6 6 n/2 x tCYC* 6 n/2 x tCYC* 6 Unit ns ns ns ns ns ns ns ns ns Remarks
DREQ input pulse width tDRWH DACK delay time (Normal bus) (Normal DRAM) EOP delay time (Normal bus) (Normal DRAM) DACK delay time (Single DRAM) (Hyper DRAM) EOP delay time (Single DRAM) (Hyper DRAM) tCLDL tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH
*: For information on tCYC (a cycle time of peripheral system clock), see "(3) Clock Output Timing."
tCYC CLK 2.4 V 2.4 V
0.8 V
0.8 V
DACK0 to DACK2 EOP0 to EOP2 (Normal bus) (Normal DRAM) DACK0 to DACK2 EOP0 to EOP2 (Single DRAM) (Hyper DRAM) tCHDL tCHEL
tCLDL tCLEL 0.8 V
tCLDH tCLEH 2.4 V
0.8 V
2.4 V
tCHDH,tCHEH
tDRWH DREQ0 to DREQ2 2.4 V 2.4 V
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6. A/D Converter Block Electrical Characteristics
(VCC = AVCC = 3.15 V to 3.6 V, VSS = AVSS = 0.0 V, AVRH = 3.15 V to 3.6 V, TA = 0C to +70C) Parameter Resolution Total error Linearity error Differentiation linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Conversion variance between channels IA IAH IR IRH -- Symbol -- -- -- -- VOT VFST -- IAIN VAIN -- Pin name -- -- -- -- AN0 to AN3 AN0 to AN3 -- AN0 to AN3 AN0 to AN3 AVRH AVCC AVCC AVRH AVRH AN0 to AN3 Value Min. -- -- -- -- -1.5LSB AVRH - 4.5LSB 5.19 *1 -- AVSS AVSS -- -- -- -- -- Typ. 10 -- -- -- +0.5LSB AVRH - 1.5LSB -- 0.1 -- -- 4 -- 110 -- -- Max. 10 3.0 2.5 1.9 +2.5LSB AVRH + 0.5LSB -- 10 AVRH AVCC -- 5 *2 -- 5 *2 4 Unit bit LSB LSB LSB mV mV s A V V mA A A A LSB
*1: VCC = AVCC = 3.15 V to 3.6 V, machine clock 25 MHz *2: Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.6 V)
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7. A/D Converter Glossary
* Resolution The smallest change in analog voltage detected by A/D converter. * Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000 0000" "00 0000 0001") to the full-scale transition point (between "11 1111 1110" "11 1111 1111"). * Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage. * Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error 3FF 1.5 LSB 3FE Actual conversion characteristic 3FD Digital output {1 LSB x (N - 1) + 0.5 LSB}
004 003 002 001 VNT (measured value) Actual conversion characteristic Ideal characteristic
0.5 LSB AVRL Analog input AVRH
Total error of digital output N =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB
[LSB]
VOT VFST
(ideal value) = AVRL + 0.5 LSB [V] (ideal value) = AVRL - 1.5 LSB [V]
VNT: A voltage for causing transition of digital output from (N - 1) to N
(Continued)
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(Continued)
Linearity error 3FF 3FE {1 LSB x (N - 1) + VOT} 3FD Digital output VFST (measured value) 004 003 002 Ideal characteristic 001 VOT (measured value) AVRL Analog input AVRH AVRL Analog input N-2 Actual conversion characteristic AVRH VNT (measured value) Actual conversion characteristic Digital output N Actual characteristic Differential linearity error
Actual conversion characteristic N+1
Ideal characteristic
N-1 V(N + 1)T VNT (measured value) (measured value)
Linearity error of = digital output N
VNT - {1 LSB x (N - 1) + VOT} 1 LSB
[LSB]
Differential linearity error of digital output N =
V(N + 1)T - VNT 1 LSB
-1 [LSB]
1 LSB =
VFST - VOT 1022
[V] AVRH - AVRL 1022
1 LSB (ideal value) =
[V]
VOT: A voltage for causing transition of digital output from (000)H to (001)H VFST: A voltage for causing transition of digital output from (3FE)H to (3FF)H VNT: A voltage for causing transition of digital output from (N - 1)H to N
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8. Notes on Using A/D Converter
Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 7 k. If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling (sampling time is 5.6 s for a machine clock of 25 MHz).
* Analog input Equivalent Circuit
Sample hold circuit Analog input pin C0 Comparator RON1 RON1: 5 k RON2: 620 k RON3: 620 k RON4: 620 k C0: 2 pF C1: 2 pF RON2 RON3 RON4 C1
* Error As the absolute value of |AVRH - AVRL| decreases, relative error increases.
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s EXAMPLE CHARACTERISTICS
(1) "H" Level Output Voltage (2) "L" Level Output Voltage
VOH (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -1 -2 -3
VOH-IOH VCC = 3.6 V VCC = 3.3 V VCC = 3.0 V VCC = 2.7 V
VOL (V) 0.25 0.20 0.15 0.10 0.05 TA = +25C 0.00
VOL-IOL VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V
TA = +25C -8 IOH (mA) 1 2 3 4 5 6 7 8 IOL (mA)
-4
-5
-6
-7
(3) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input)
(4) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input)
VIN (V) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.4 2.7 TA = +25C
VIN-VCC
VIN (V) 2.4 2.2 VIH VIL 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.4 2.7 TA = +25C
VIN-VCC VIH
VIL
3.0
3.3
3.6 VCC (V)
3.0
3.3
3.6 VCC (V)
VIH: Threshold when input voltage is set to "H" Level. VIL: Threshold when input voltage is set to "L" Level.
VIH: Threshold when input voltage in hysteresis characteristics is set to "H" Level. VIL: Threshold when input voltage in hysteresis characteristics is set to "L" Level.
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(5) Power Supply Current (fcp = Internal clock frequency)
ICC (mA) ICC-VCC 100 TA = +25C 90 80 70 60 50 40 30 20 10 0 2.7 3.0 3.3 3.6
fCP = 25 MHz fCP = 20 MHz
ICCS (mA) ICCS-VCC 50 TA = +25C 45 40 35 30 25 20 15 10 5
fCP = 25 MHz fCP = 20 MHz
3.9 VCC (V)
0 2.7
3.0
3.3
3.6
3.9 VCC (V)
ICCH(A) 2.0 TA = +25C 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.7 IR(A) 130 125 120 115 110 105 100 95 90 85 80 2.7 3.0 TA = +25C 3.0
ICCH-VCC
IA (mA) IA-AVCC 2.5 TA = +25C 2.0
1.5
1.0
0.5
3.3
3.6 VCC (V)
0.0 2.7
3.0
3.3
3.6
3.9 AVCC (V)
IR-AVCC
(6) Pull-up Resistance
R (k) 100 R-VCC TA = +25C
3.3
3.6
3.9 AVCC (V)
10
2.7
3.0
3.3
3.6
3.9 VCC (V)
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s INSTRUCTIONS (165 INSTRUCTIONS)
1. How to Read Instruction Set Summary
Mnemonic ADD * ADD Rj, Ri #s5, Ri , , (2) Type A C , , (3) OP A6 A4 , , (4) CYC 1 1 , , (5) NZVC CCCC CCCC , , (6) Operation Ri + Rj Ri Ri + s5 Ri , , (7) Remarks
(1)
(1) Names of instructions Instructions marked with * are not included in CPU specifications. These are extended instruction codes added/extended at assembly language levels. (2) Addressing modes specified as operands are listed in symbols. Refer to "2. Addressing mode symbols" for further information. (3) Instruction types (4) Hexa-decimal expressions of instructions (5) The number of machine cycles needed for execution a: Memory access cycle and it has possibility of delay by Ready function. b: Memory access cycle and it has possibility of delay by Ready function. If an object register in a LD operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or if the instruction belongs to instruction format A group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. For a, b, c and d, minimum execution cycle is 1. (6) Change in flag sign * Flag change C : Change - : No change 0 : Clear 1 : Set * Flag meanings N : Negative flag Z : Zero flag V : Over flag C : Carry flag (7) Operation carried out by instruction
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2. Addressing Mode Symbols
: Register direct (R0 to R15, AC, FP SP) , : Register direct (R0 to R15, AC, FP SP) , : Register direct (R13, AC) : Register direct (Program status register) : Register direct (TBR, RP SSP USP MDH, MDL) , , , : Register direct (CR0 to CR15) : Register direct (CR0 to CR15) : Unsigned 8-bit immediate (-128 to 255) Note: -128 to -1 are interpreted as 128 to 255 #i20 : Unsigned 20-bit immediate (-0X80000 to 0XFFFFF) Note: -0X7FFFF to -1 are interpreted as 0X7FFFF to 0XFFFFF #i32 : Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF) Note: -0X80000000 to -1 are interpreted as 0X80000000 to 0XFFFFFFFF #s5 : Signed 5-bit immediate (-16 to 15) #s10 : Signed 10-bit immediate (-512 to 508, multiple of 4 only) #u4 : Unsigned 4-bit immediate (0 to 15) #u5 : Unsigned 5-bit immediate (0 to 31) #u8 : Unsigned 8-bit immediate (0 to 255) #u10 : Unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : Unsigned 8-bit direct address (0 to 0XFF) @dir9 : Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only) @dir10 : Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only) label9 : Signed 9-bit branch address (-0X100 to 0XFC, multiple of 2 only) label12 : Signed 12-bit branch address (-0X800 to 0X7FC, multiple of 2 only) label20 : Signed 20-bit branch address (-0X80000 to 0X7FFFF) label32 : Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF) @Ri : Register indirect (R0 to R15, AC, FP SP) , @Rj : Register indirect (R0 to R15, AC, FP SP) , @(R13, Rj) : Register relative indirect (Rj: R0 to R15, AC, FP SP) , @(R14, disp10) : Register relative indirect (disp10: -0X200 to 0X1FC, multiple of 4 only) @(R14, disp9) : Register relative indirect (disp9: -0X100 to 0XFE, multiple of 2 only) @(R14, disp8) : Register relative indirect (disp8: -0X80 to 0X7F) @(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only) @Ri+ : Register indirect with post-increment (R0 to R15, AC, FP SP) , @R13+ : Register indirect with post-increment (R13, AC) @SP+ : Stack pop @-SP : Stack push (reglist) : Register list Ri Rj R13 Ps Rs CRi CRj #i8
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3. Instruction Types
MSB 16 bits OP 8 Rj 4 Ri 4 LSB
Type A
Type B
OP 4
i8/o8 8
Ri 4
Type C
OP 8
u4/m4 4
Ri 4
ADD, ADDN, CMP, LSL, LSR and ASR instructions only Type *C' OP 7 s5/u5 5 Ri 4
Type D
OP 8
u8/rel8/dir/reglist 8
Type E
OP 8
SUB-OP 4
Ri 4
Type F
OP 5
rel11 11
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4. Detailed Description of Instructions
* Add/subtract operation instructions (10 instructions) Mnemonic ADD * ADD ADD ADD2 ADDC ADDN * ADDN ADDN ADDN2 SUB SUBC SUBN Rj, Ri #s5, Ri #i4, Ri #i4, Ri Rj, Ri Rj, Ri #s5, Ri #i4, Ri #i4, Ri Rj, Ri Rj, Ri Rj, Ri
Type
OP A6 A4 A4 A5 A7 A2 A0 A0 A1 AC AD AE
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1
Operation
Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension Add operation with sign MSB is interpreted as a sign in assembly language Zero-extension Sign-extension
A C' C C A A C' C C A A A
C C C C Ri + Rj Ri C C C C Ri + s5 Ri C C C C Ri + extu (i4) Ri C C C C Ri + extu (i4) Ri C C C C Ri + Rj + c Ri - - - - Ri + Rj Ri - - - - Ri + s5 Ri - - - - Ri + extu (i4) Ri - - - - Ri + extu (i4) Ri C C C C Ri - Rj Ri C C C C Ri - Rj - c Ri - - - - Ri - Rj Ri
Subtract operation with carry
* Compare operation instructions (3 instructions) Mnemonic CMP * CMP CMP CMP2 Rj, Ri #s5, Ri #i4, Ri #i4, Ri
Type
OP AA A8 A8 A9
Cycle N Z V C 1 1 1 1
Operation
Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension
A C' C C
C C C C Ri - Rj C C C C Ri - s5 C C C C Ri + extu (i4) C C C C Ri + extu (i4)
* Logical operation instructions (12 instructions) Mnemonic AND AND ANDH ANDB OR OR ORH ORB EOR EOR EORH EORB Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri
Type
OP 82 84 85 86 92 94 95 96 9A 9C 9D 9E
Cycle N Z V C 1 1 + 2a 1 + 2a 1 + 2a 1 1 + 2a 1 + 2a 1 + 2a 1 1 + 2a 1 + 2a 1 + 2a CC CC CC CC CC CC CC CC CC CC CC CC - - - - - - - - - - - - - - - - - - - - - - - - Ri & (Ri) & (Ri) & (Ri) & Ri (Ri) (Ri) (Ri) | | | |
Operation = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj
Remarks Word Word Half word Byte Word Word Half word Byte Word Word Half word Byte
A A A A A A A A A A A A
Ri ^ (Ri) ^ (Ri) ^ (Ri) ^
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* Bit manipulation arithmetic instructions (8 instructions) Mnemonic BANDL BANDH * BAND BORL BORH * BOR BEORL BEORH * BEOR BTSTL BTSTH #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH)
Type
OP 80 81
Cycle N Z V C
Operation
Remarks Manipulate lower 4 bits Manipulate upper 4 bits
C C *1 C C *2 C C *3 C C
1 + 2a - - - - (Ri) & = (F0H + u4) 1 + 2a - - - - (Ri) & = ((u4<<4) + 0FH) - - - - - (Ri) & = u8
90 91
1 + 2a - - - - (Ri) | = u4 1 + 2a - - - - (Ri) | = (u4<<4) - - - - - (Ri) | = u8
Manipulate lower 4 bits Manipulate upper 4 bits
98 99
1 + 2a - - - - (Ri) ^ = u4 1 + 2a - - - - (Ri) ^ = (u4<<4) - - - - - (Ri) ^ = u8 0 C - - (Ri) & u4 C C - - (Ri) & (u4<<4)
Manipulate lower 4 bits Manipulate upper 4 bits
88 89
2+a 2+a
Test lower 4 bits Test upper 4 bits
*1: Assembler generates BANDL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BANDH if "u8&0xF0" leaves an active bit. Depending on the value in the "u8" format, both BANDL and BANDH may be generated. *2: Assembler generates BORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BORH if "u8&0xF0" leaves an active bit. *3: Assembler generates BEORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BEORH if "u8&0xF0" leaves an active bit. * Add/subtract operation instructions (10 instructions) Mnemonic MUL MULU MULH MULUH DIVOS DIVOU DIV1 DIV2 DIV3 DIV4S * DIV * DIVU Rj, Ri Rj, Ri Rj, Ri Rj, Ri Ri Ri Ri Ri Ri Ri *1 *2
Type
OP AF AB BF BB 97 - 4 97 - 5 97 - 6 97 - 7 9F - 6 9F - 7
Cycle N Z V C 5 5 3 3 1 1 d 1 1 1 - - CCC CCC CC- CC- - - - - - - - - - C C - - C - - - - - - - - - - -
Operation Rj x Ri MDH, MDL Rj x Ri MDH, MDL Rj x Ri MDL Rj x Ri MDL
Remarks 32-bit x 32-bit = 64-bit Unsigned 16-bit x 16-bit = 32-bit Unsigned Step calculation 32-bit/32-bit = 32-bit
A A A A E E E E E E
- - C C - - C MDL/Ri MDL, MDL%Ri MDH - C - C MDL/Ri MDL, MDL%Ri MDH
Unsigned
*1: DIVOS, DIV1 x 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes. *2: DIVOU and DIV1 x 32 are generated. A total instruction code length of 66 bytes.
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* Shift arithmetic instructions (9 instructions) Mnemonic LSL * LSL LSL LSL2 LSR * LSR LSR LSR2 ASR * ASR ASR ASR2 Rj, Ri #u5, Ri #u4, Ri #u4, Ri Rj, Ri #u5, Ri #u4, Ri #u4, Ri Rj, Ri #u5, Ri #u4, Ri #u4, Ri
Type
OP B6 B4 B4 B5 B2 B0 B0 B1 BA B8 B8 B9
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 CC CC CC CC CC CC CC CC CC CC CC CC - - - - - - - - - - - - C C C C C C C C C C C C
Operation Ri<>Rj Ri Ri>>u5 Ri Ri>>u4 Ri Ri>>(u4 + 16) Ri Ri>>Rj Ri Ri>>u5 Ri Ri>>u4 Ri Ri>>(u4 + 16) Ri
Remarks Logical shift
A C' C C A C' C C A C' C C
Logical shift
Logical shift
* Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) Mnemonic LDI: 32 LDI: 20 LDI: 8 * LDI #i32, Ri #i20, Ri #i8, Ri # {i8 | i20 | i32}, Ri *1
Type
OP 9F - 8 9B C0
Cycle N Z V C 3 2 1
Operation
Remarks Upper 12 bits are zeroextended Upper 24 bits are zeroextended
E C B
- - - - i32 Ri - - - - i20 Ri - - - - i8 Ri {i8 | i20 | i32} Ri
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. If an immediate value contains relative value or external reference, assembler selects i32. * Memory load instructions (13 instructions) Mnemonic LD LD LD LD LD LD LD LDUH LDUH LDUH LDUB LDUB LDUB @Rj, Ri @(R13, Rj), Ri @(R14, disp10), Ri @(R15, udisp6), Ri @R15 +, Ri @R15 +, Rs @R15 +, PS @Rj, Ri @(R13, Rj), Ri @(R14, disp9), Ri @Rj, Ri @(R13, Rj), Ri @(R14, disp8), Ri
Type
OP 04 00 20 03 07 - 0 07 - 8 07 - 9 05 01 40 06 02 60
Cycle N Z V C b b b b b b
1+a+b
Operation (Rj) Ri (R13 + Rj) Ri (R14 + disp10) Ri (R15 + udisp6) Ri (R15) Ri, R15 + = 4 (R15) Rs, R15 + = 4
Remarks
A A B C E E E A A B A A B
- - - - - -
- - - - - -
- - - - - -
- - - - - -
C C C C (R15) PS, R15 + = 4 - - - - (Rj) Ri - - - - (R13 + Rj) Ri - - - - (R14 + disp9) Ri - - - - (Rj) Ri - - - - (R13 + Rj) Ri - - - - (R14 + disp8) Ri
Rs: Special-purpose register Zero-extension Zero-extension Zero-extension Zero-extension Zero-extension Zero-extension
b b b b b b
Note :The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 o8 = disp8:Each disp is a code extension. disp9 o8 = disp9>>1:Each disp is a code extension. disp10 o8 = disp10>>2:Each disp is a code extension. udisp6 u4 = udisp6>>2:udisp4 is a 0 extension. 104
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* Memory store instructions (13 instructions) Mnemonic ST ST ST ST ST ST ST STH STH STH STB STB STB Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp10) Ri, @(R15, udisp6) Ri, @-R15 Rs, @-R15 PS, @-R15 Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp9) Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp8)
Type
OP 14 10 30 13 17 - 0 17 - 8 17 - 9 15 11 50 16 12 70
Cycle N Z V C a a a a a a a a a a a a a - - - - - - - - - - - - - - - - - - - - - - - -
Operation Ri (Rj) Ri (R13 + Rj) Ri (R14 + disp10) Ri (R15 + usidp6) R15 - = 4, Ri (R15) R15 - = 4, Rs (R15) Word Word Word
Remarks
A A B C E E E A A B A A B
- - - - R15 - = 4, PS (R15) - - - - Ri (Rj) - - - - Ri (R13 + Rj) - - - - Ri (R14 + disp9) - - - - Ri (Rj) - - - - Ri (R13 + Rj) - - - - Ri (R14 + disp8)
Rs: Special-purpose register Half word Half word Half word Byte Byte Byte
Note :The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 o8 = disp8:Each disp is a code extension. disp9 o8 = disp9>>1:Each disp is a code extension. disp10 o8 = disp10>>2:Each disp is a code extension. udisp6 u4 = udisp6>>2:udisp4 is a 0 extension. * Transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) Mnemonic MOV MOV MOV MOV MOV Rj, Ri Rs, Ri Ri, Rs PS, Ri Ri, PS
Type
OP 8B B7 B3 17 - 1 07 - 1
Cycle N Z V C 1 1 1 1 c
Operation
Remarks Transfer between general-purpose registers Rs: Special-purpose register Rs: Special-purpose register
A A A E E
- - - - Rj Ri - - - - Rs Ri - - - - Ri Rs - - - - PS Ri C C C C Ri PS
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* Non-delay normal branch instructions (23 instructions) Mnemonic JMP CALL CALL RET INT #u8 @Ri label12 @Ri
Type
OP 97 - 0 D0 97 - 1 97 - 2 1F
Cycle N Z V C 2 2 2 2 3+3a - - - - Ri PC
Operation
Remarks
E F E E D
- - - - PC + 2 RP , PC + 2 + rel11 x 2 PC - - - - PC + 2 RP Ri PC , - - - - RP PC - - - - SSP - = 4, PS (SSP), SSP - = 4, PC + 2 (SSP), 0 I flag, 0 S flag, (TBR + 3FC - u8 x 4) PC Return
INTE
E
9F - 3 3 + 3a - - - - SSP - = 4, PS (SSP), For emulator SSP - = 4, PC + 2 (SSP), 0 S flag, (TBR + 3D8 - u8 x 4) PC 97 - 3 2 + 2a C C C C (R15) PC, R15 - = 4, (R15) PS, R15 - = 4 E1 E0 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF 1 2 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Non-branch PC + 2 + rel8 x 2 PC PCif Z = = 1 PCif Z = = 0 PCif C = = 1 PCif C = = 0 PCif N = = 1 PCif N = = 0 PCif V = = 1 PCif V = = 0 PCif V xor N = = 1 PCif V xor N = = 0 PCif (V xor N) or Z = = 1 PCif (V xor N) or Z = = 0 PCif C or Z = = 1 PCif C or Z = = 0
RETI BNO BRA BEQ BNE BC BNC BN BP BV BNV BLT BGE BLE BGT BLS BHI label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9
E D D D D D D D D D D D D D D D D
Notes: * "2/1" in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. * The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 rel8 = (label9 - PC - 2)/2 label12 rel11 = (label12 - PC - 2)/2 * RETI must be operated while S flag = 0.
106
MB91F109
* Branch instructions with delays (20 instructions) Mnemonic JMP:D CALL:D CALL:D RET:D BNO:D BRA:D BEQ:D BNE:D BC:D BNC:D BN:D BP:D BV:D BNV:D BLT:D BGE:D BLE:D BGT:D BLS:D BHI:D label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 @Ri label12 @Ri
Type
OP 9F - 0 D8 9F - 1 9F - 2 F1 F0 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Operation
Remarks
E F E E D D D D D D D D D D D D D D D D
- - - - Ri PC - - - - PC + 4 RP , PC + 2 + rel11 x 2 PC - - - - PC + 4 RP Ri PC , - - - - RP PC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Non-branch PC + 2 + rel8 x 2 PC PCif Z = = 1 PCif Z = = 0 PCif C = = 1 PCif C = = 0 PCif N = = 1 PCif N = = 0 PCif V = = 1 PCif V = = 0 PCif V xor N = = 1 PCif V xor N = = 0 PCif (V xor N) or Z = = 1 PCif (V xor N) or Z = = 0 PCif C or Z = = 1 PCif C or Z = = 0 Return
Notes: * The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 rel8 = (label9 - PC - 2)/2 label12 rel11 = (label12 - PC - 2)/2 * Delayed branch operation always executes next instruction (delay slot) before making a branch. * Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other instruction is stored, this device may operate other operation than defined. The instruction described "1" in the other cycle column than branch instruction. The instruction described "a", "b", "c" or "d" in the cycle column.
107
MB91F109
* Direct addressing instructions Mnemonic DMOV DMOV DMOV DMOV DMOV DMOV DMOVH DMOVH DMOVH DMOVH DMOVB DMOVB DMOVB DMOVB @dir10, R13, @dir10, @R13+, @dir10, @R15+, @dir9, R13, @dir9, @R13+, @dir8, R13, @dir8, @R13+, R13 @dir10 @R13+ @dir10 @-R15 @dir10 R13 @dir9 @R13+ @dir9 R13 @dir8 @R13+ @dir8
Type
OP 08 18 0C 1C 0B 1B 09 19 0D 1D 0A 1A 0E 1E
Cycle N Z V C b a 2a 2a 2a 2a b a 2a 2a b a 2a 2a - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Operation (dir10) R13 R13 (dir10) (dir10) (R13), R13 + = 4 (R13) (dir10), R13 + = 4 R15 - = 4, (dir10) (R15) (R15) (dir10), R15 + = 4 (dir9) R13 R13 (dir9) (dir9) (R13), R13 + = 2 (R13) (dir9), R13 + = 2 (dir8) R13 R13 (dir8) (dir8) (R13), R13 + + (R13) (dir8), R13 + + Word Word Word Word Word Word
Remarks
D D D D D D D D D D D D D D
Half word Half word Half word Half word Byte Byte Byte Byte
Note :The relations between the dir field of TYPE-D in the instruction format and the assembler description from disp8 to disp10 are as follows: disp8 dir + disp8:Each disp is a code extension disp9 dir = disp9>>1:Each disp is a code extension disp10 dir = disp10>>2:Each disp is a code extension * Resource instructions (2 instructions) Mnemonic LDRES STRES @Ri+, #u4, #u4 @Ri+
Type
OP BC BD
Cycle N Z V C a a
Operation
Remarks u4: Channel number u4: Channel number
C C
- - - - (Ri) u4 resource Ri + = 4 - - - - u4 resource (Ri) Ri + = 4
* Co-processor instructions (4 instructions) Mnemonic COPOP COPLD COPST COPSV #u4, #CC, CRj, CRi #u4, #CC, Rj, CRi #u4, #CC, CRj, Ri #u4, #CC, CRj, Ri
Type
OP 9F - C 9F - D 9F - E 9F - F
Cycle N Z V C 2+a 1 + 2a 1 + 2a 1 + 2a - - - - - - - - - - - - - - - -
Operation Calculation Rj CRi CRj Ri CRj Ri
Remarks
E E E E
No error traps
108
MB91F109
* Other instructions (16 instructions) Mnemonic NOP ANDCCR #u8 ORCCR #u8 STILM ADDSP EXTSB EXTUB EXTSH EXTUH LDM0 LDM1 * LDM STM0 STM1 * STM2 ENTER #u8 #s10 Ri Ri Ri Ri (reglist) (reglist) (reglist) (reglist) (reglist) (reglist) #u10 *5 *2 D 0F *3 D D 8E 8F *1
Type
OP 9F - A 83 93 87 A3 97 - 8 97 - 9 97 - A 97 - B 8C 8D
Cycle N Z V C 1 c c 1 1 1 1 1 1 *4 *4 - *
6
Operation
Remarks
E D D D D E E E E D D
- - - - No changes C C C C CCR and u8 CCR C C C C CCR or u8 CCR - - - - i8 ILM - - - - R15 + = s10 - - - - - - - - - - - - - - - - Sign extension 8 32 bits Zero extension 8 32 bits Sign extension 16 32 bits Zero extension 16 32 bits Load-multi R0 to R7 Load-multi R8 to R15 Load-multi R0 to R15 Store-multi R0 to R7 Store-multi R8 to R15 Store-multi R0 to R15 Entrance processing of function Exit processing of function For SEMAFO management Byte data Set ILM immediate value ADD SP instruction
- - - - (R15) reglist, R15 increment - - - - (R15) reglist, R15 increment - - - - (R15 + +) reglist, - - - - R15 decrement, reglist (R15) - - - - R15 decrement, reglist (R15) - - - - reglist (R15 + +) - - - - R14 (R15 - 4), R15 - 4 R14, R15 - u10 R15 - - - - R14 + 4 R15, (R15 - 4) R14 - - - - Ri TEMP , (Rj) Ri, TEMP (Rj)
*6 - 1+a
LEAVE XCHB @Rj, Ri
E A
9F - 9 8A
b 2a
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler description s10 is as follows. s10 s8 = s10>>2 *2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler description u10 is as follows. u10 u8 = u10>>2 *3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified, assembler generates LDM1. Both LDM0 and LDM1 may be generated. *4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following calculation; a x (n - 1) + b + 1 when "n" is number of registers specified. *5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified, assembler generates STM1. Both STM0 and STM1 may be generated. *6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following calculation; a x n + 1 when "n" is number of registers specified.
109
MB91F109
* 20-bit normal branch macro instructions Mnemonic * CALL20 * BRA20 * BEQ20 * BNE20 * BC20 * BNC20 * BN20 * BP20 * BV20 * BNV20 * BLT20 * BGE20 * BLE20 * BGT20 * BLS20 * BHI20 label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri Operation Next instruction address RP label20 PC , label20 PC if (Z = = 1) then label20 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL20 (1) If label20 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL @Ri *2: BRA20 (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP @Ri *3: Bcc20 (BEQ20 to BHI20) (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP @Ri false:
110
MB91F109
* 20-bit delayed branch macro instructions Mnemonic * CALL20:D label20, Ri * BRA20:D * BEQ20:D * BNE20:D * BC20:D * BNC20:D * BN20:D * BP20:D * BV20:D * BNV20:D * BLT20:D * BGE20:D * BLE20:D * BGT20:D * BLS20:D * BHI20:D label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri Operation Next instruction address + 2 RP label20 PC , label20 PC if (Z = = 1) then label20 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL20:D (1) If label20 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL:D @Ri *2: BRA20:D (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP:D @Ri *3: Bcc20:D (BEQ20:D to BHI20:D) (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP:D @Ri false:
111
MB91F109
* 32-bit normal macro branch instructions Mnemonic * CALL32 * BRA32 * BEQ32 * BNE32 * BC32 * BNC32 * BN32 * BP32 * BV32 * BNV32 * BLT32 * BGE32 * BLE32 * BGT32 * BLS32 * BHI32 label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri Operation Next instruction address RP label32 PC , label32 PC if (Z = = 1) then label32 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL32 (1) If label32 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL @Ri *2: BRA32 (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP @Ri *3: Bcc32 (BEQ32 to BHI32) (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP @Ri false:
112
MB91F109
* 32-bit delayed macro branch instructions Mnemonic * CALL32:D label32, Ri * BRA32:D * BEQ32:D * BNE32:D * BC32:D * BNC32:D * BN32:D * BP32:D * BV32:D * BNV32:D * BLT32:D * BGE32:D * BLE32:D * BGT32:D * BLS32:D * BHI32:D label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri Operation Next instruction address + 2 RP label32 PC , label32 PC if (Z = = 1) then label32 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL32:D (1) If label32 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL:D @Ri *2: BRA32:D (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP:D @Ri *3: Bcc32:D (BEQ32:D to BHI32:D) (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP:D @Ri false:
113
MB91F109
s ORDERING INFORMATION
Part number MB91F109PFV-XXX MB91F109PF-XXX Package 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) Remarks
114
MB91F109
s PACKAGE DIMENSIONS
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
1.50 -0.10
51
+0.20 +.008
(Mouting height)
14.000.10(.551.004)SQ
.059 -.004
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 +.002
"A" 0.50(.0197)TYP 0.18 -0.03 .007
+0.08 +.003 -.001
0.40(.016)MAX 0.127 -0.02 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
2000 FUJITSU LIMITED F100007S-2C-4
Dimensions in mm (inches)
115
MB91F109
100-pin Plastic QFP (FPT-100P-M06)
23.900.40(.941.016)
80 81
3.35(.132)MAX
51 50
20.000.20(.787.008)
0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX 0 10 0.800.20 (.031.008) Details of "B" part
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
116
MB91F109
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0009 (c) FUJITSU LIMITED Printed in Japan

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